Abstract: Systems and methods for a battery architecture include a first fuse connected between a first battery cell and a second battery cell of a battery pack, and a second fuse connected between the second battery cell and a terminal of a charge port.

Abstract: Systems, apparatuses, and methods for a host controller inferring idleness based on activity generated by a bus-attached peripheral device are disclosed. A host controller detects activity by a first device attached to the host controller via a first bus. The host controller generates an activity vector based on the detected activity, and the host controller determines whether the activity vector indicates that the first device is only engaging in handshaking or control activity rather than data transfer. If the first device is merely communicating status information, then the host controller infers idleness and conveys an idleness indicator to a power manager. The power manager turns off power to system memory and/or other components based on the idleness indicator, but keeps enough power on to allow the host controller to communicate with the first device for handshaking or status purposes.

Abstract: A processing system isolates at a physically or logically separate memory region of a processing unit boot code that is received from an external boot source for programming a boot memory of the processing unit until after the boot code is validated to protect against buffer overruns that could compromise the processing system. The processing unit includes a secure buffer region of memory that is physically or logically isolated from the remainder of the processing unit for receiving boot code from an external boot source such as a personal computer (PC) such that any buffer overruns at the secure buffer simply overwrite data stored at the secure buffer, and do not affect data or instructions that are executing at the processing unit.

Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.