Patents by Inventor Joseph Schaefer

Joseph Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230342523
    Abstract: A computer-implemented method facilitates receiving, by a computing system, one or more parameters that specify attributes associated with a bonded joint and, in particular, a type of bonded joint. The computing system selects from a model template repository one or more bonded joint model templates associated with the type of bonded joint. The computing system generates a bonded joint model based on the bonded joint model templates and the parameters. The bonded joint model facilitates the performance of finite element analysis (FEA). FEA logic of the computing system simulates the application of stress to the bonded joint model. The FEA logic of the computing system determines a change in a size of a defect that results from the application of stress to the bonded joint model. The computing system determines, based on the change in the size of the defect, the life expectancy of the bonded joint.
    Type: Application
    Filed: February 16, 2023
    Publication date: October 26, 2023
    Inventors: Joseph Schaefer, Brian Justusson, Mainak Bhattacharya
  • Patent number: 8335866
    Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 18, 2012
    Assignee: Intel Corporation
    Inventors: Gary Solomon, Joseph Schaefer, Robert A. Dunstan, Brad Saunders
  • Patent number: 8321600
    Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: November 27, 2012
    Assignee: Intel Corporation
    Inventors: Gary Solomon, Joseph Schaefer, Robert A. Dunstan, Brad Saunders
  • Patent number: 7808989
    Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: October 5, 2010
    Inventors: Oleg Awsienko, Edward Butler, Gary L. McAlpine, David B. Minturn, Joseph Schaefer, Gary A. Solomon
  • Publication number: 20080144619
    Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.
    Type: Application
    Filed: November 5, 2007
    Publication date: June 19, 2008
    Inventors: Oleg Awsienko, Edward Butler, Gary L. McAlpine, David B. Minturn, Joseph Schaefer, Gary A. Solomon
  • Patent number: 7310319
    Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: December 18, 2007
    Assignee: Intel Corporation
    Inventors: Oleg Awsienko, Edward Butler, Gary L. McAlpine, David B. Minturn, Joseph Schaefer, Gary A. Solomon
  • Publication number: 20070139478
    Abstract: An ink jetting assembly includes a body, and an ink jet chip attached to the body. The ink jet chip has a mounting surface, a face surface, an ink channel extending to the face surface, and at least one actuator associated with the ink channel. The actuator includes a plurality of electrical contact pads formed on the face surface. A plurality of passageways extends through the ink jet chip from the mounting surface to the face surface. The ink jetting assembly also includes a plurality of electrodes. Each of the plurality of electrodes passes through a respective passageway of the plurality of passageways and is electrically connected to a respective contact pad of the plurality of electrical contact pads at the face surface.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventors: John Fowler, Ganesh Phatak, Matthew Russell, Jeffrey Sangalli, Joseph Schaefer, David Ward
  • Patent number: 7120711
    Abstract: A system having an I/O interconnect topology utilizes internal packetized communications. The system includes a host system element, a plurality of switching elements, and a root complex to bridge communications between the host system and the switching elements. The ports of at least some of the switching elements have a cross-link device associated therewith, which is a logical device defined by configuration space of the switching element. Each cross-link device defines a cross-link communication path between two switching elements of the hierarchy allowing communications between peripherals to bypass the host.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: Joseph Schaefer, David B. Minturn, Prashant Sethi
  • Publication number: 20060126738
    Abstract: A method, system and program product in accordance with the preferred embodiments use motion vector data to track an object moving between areas being monitored by a plurality of video cameras. Motion vector data are used to predict whether an object in a first field of view covered by a first camera system will enter a second field of view covered by a second camera system. If the prediction is that the object will enter the second field of view, tracking data are provided to the second camera system. The tracking data may include pan, tilt and/or zoom adjustment data, which may be provided to a PTZ adjustment mechanism of the second camera system, for example. Alternatively, or in addition, the tracking data may include pan/tilt motion vector data, zoom factor data and/or shrinkage/expansion data, which are provided to a motion tracking processor of the second camera system.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 15, 2006
    Applicant: International Business Machines Corporation
    Inventors: Charles Boice, Adrian Butter, Joseph Schaefer, Edward Westermann
  • Publication number: 20060126737
    Abstract: A method, system and program product in accordance with the preferred embodiments use motion vector data to track an object being monitored by a video camera. Motion vector data are used to calculate pan, tilt and/or zoom adjustment data. For example, motion vector data may be provided to a motion tracking processor at a macroblock level by an MPEG compression processor. Alternatively, motion vector data may be provided to a motion tracking processor at a pixel level by a pre-processor. The pan, tilt and/or zoom adjustment data is sent to the camera. For example, the pan, tilt and/or zoom adjustment data may be sent to a PTZ adjustment mechanism of the camera. Because the preferred embodiments use a closed loop system, tracking the object is made easier and does not require a skilled operator.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 15, 2006
    Applicant: International Business Machines Corporation
    Inventors: Charles Boice, Adrian Butter, Joseph Schaefer, Edward Westermann
  • Publication number: 20060062292
    Abstract: An encode control strategy is provided for variable bit rate encoding of a sequence of video frames in a single pass. The control strategy includes determining whether a video frame has a complexity level statistically outside a defined range from a complexity level of at least one preceding frame of the sequence of video frames, and if so, determining a new average bit rate target for the video frame. The new average bit rate for the video frame is determined employing at least one of spatial complexity and temporal complexity of the video frame. The new average bit rate target for the video frame is used to set frame level bit rate control parameter(s), and the video frame is encoded using the set frame level bit rate control parameter(s).
    Type: Application
    Filed: September 23, 2004
    Publication date: March 23, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles Boice, Krishna Ratakonda, Joseph Schaefer, Joseph Underwood
  • Publication number: 20050086549
    Abstract: A switching fabric handles transactions using a protocol that directs packets based on path routing information. Components participate in transactions using a protocol that issues packets based on physical location of a destination device over the switching fabric, by establishing a virtual link partner relationship between the components.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 21, 2005
    Inventors: Gary Solomon, Edward Butler, Joseph Schaefer
  • Publication number: 20050055484
    Abstract: A method and an apparatus to configure a multi-port device are disclosed. The method includes defining a first set of pointers, one for each port of the multi-port device, and storing the first set of pointers in one or more capability structures of the multi-port device.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 10, 2005
    Inventors: Peter Iskiyan, Joseph Schaefer, Gary Solomon
  • Publication number: 20050041658
    Abstract: A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.
    Type: Application
    Filed: December 23, 2003
    Publication date: February 24, 2005
    Inventors: David Mayhew, Todd Comins, Lynne Brocco, Joseph Schaefer, Gary Solomon, Edward Butler
  • Publication number: 20050030963
    Abstract: A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.
    Type: Application
    Filed: December 23, 2003
    Publication date: February 10, 2005
    Inventors: Gary Solomon, Edward Butler, Joseph Schaefer, David Mayhew, Todd Comins, Lynne Brocco
  • Publication number: 20040123014
    Abstract: A system having an I/O interconnect topology utilizes internal packetized communications. The system includes a host system element, a plurality of switching elements, and a root complex to bridge communications between the host system and the switching elements. The ports of at least some of the switching elements have a cross-link device associated therewith, which is a logical device defined by configuration space of the switching element. Each cross-link device defines a cross-link communication path between two switching elements of the hierarchy allowing communications between peripherals to bypass the host.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Joseph Schaefer, David B. Minturn, Prashant Sethi
  • Publication number: 20030086421
    Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.
    Type: Application
    Filed: November 2, 2001
    Publication date: May 8, 2003
    Inventors: Oleg Awsienko, Edward Butler, Gary L. McAlpine, David B. Minturn, Joseph Schaefer, Gary A. Solomon
  • Patent number: D513460
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: January 10, 2006
    Assignee: Kentain Products Ltd.
    Inventors: Glen Lippert, Scott Lippert, Joseph Schaefer