Abstract: A waveguide device is provided. The device comprises a semiconductor waveguide structure and at least one charge storing structure. Said at least one charge storing structure is configured to apply selected electric field on the semiconductor waveguide structure to thereby vary refractive index within said semiconductor waveguide structure. Wherein the charge storing structure comprises a charge trapping layer configured for storing charge carriers configured for selectively generating constant electric field of a predetermined magnitude. The device may be used in optical resonators, interferometer for optical and optoelectronic applications, capable of desirably varying refractive index within the waveguide structure.

Abstract: A photovoltaic device is presented including one or more cell units. The photovoltaic device comprises a semiconductor substrate having a patterned light collecting surface defining an array of spaced-apart substantially parallel first grooves. Each of these first grooves has a bottom portion, comprising a bottom surface and side walls extending from the bottom portion and being substantially perpendicular to the surface of the device. A heavily doped semiconductor layer in the form of spaced-apart regions is located at the bottom surfaces of the first grooves respectively. Further improvement of performance is obtained by deposition of thin metal lines on top of the heavily doped spaced apart lines.

Abstract: The present invention provides a volumetric solar structure comprising one or more solar cells. The solar structure comprises a semiconductor substrate of a first conductivity type having a patterned surface thereof, the pattern defining an array of spaced-apart grooves of a funnel-like shape, and a second opposite conductivity type material layer positioned on at least a part of the patterned surface of the substrate. The structure thereby defines junction regions, in which charge carriers are generated by incident radiation energy to which the structure is exposed. The junction regions are located at different heights upon the patterned surface of the substrate.

Abstract: The present invention provides a surface-substrate for adherence of cells thereto. The surface-substrate comprises at least one micronail structure protruding from the surface, at least a region of the micronail having cellular-internalization promoting properties. The invention also provides an electronic device comprising a transistor structure, in which a gate electrode is formed with the at least one micronail protruding from the surface thereof.

Abstract: The present invention provides a surface-substrate for adherence of cells thereto. The surface-substrate comprises at least one micronail structure protruding from the surface, at least a region of the micronail having cellular-internalization promoting properties. The invention also provides an electronic device comprising a transistor structure, in which a gate electrode is formed with the at least one micronail protruding from the surface thereof.

Abstract: An integrated thermal imager for detecting combined passive LWIR or MWIR radiation of a scene and active SWIR radiation of a laser source is described The imager includes a two-dimensional focal plane array (2D-FPA) constituted by an assembly of voltage tunable photodetectors. Each voltage tunable photodetector integrates a quantum well infrared photodetector (QWIP) together with a heterojunction bipolar phototransistor (HBPT), thereby forming a pixel element in the 2D-FPA.

Abstract: A device and method are presented for detecting analyte molecules in a medium. At least one FET (Field Effect Transistor) is provided being formed by at least one pair of source-drain electrodes and at least one gate electrode. The gate electrode is coated with a layer of receptor molecules that in the presence of said analytes catalyze a reaction that causes release of ions in a medium surrounding said receptor molecules. A monolayer of linker molecules is provided for linking said receptor molecules to said at least one gate such that a distance between the receptor molecules layer and the surface of the coated gate is smaller than 15A. In the prefered embodiments, the receptor molecules are enzymes (e.g. acetylcholine estarase) or peptides, and the analyte molecules are pesticides, herbicides and chemical pollutants of industrial origin.

Abstract: Apparatus including a substrate, having a substrate surface; an object having a maximum dimension smaller than 1 mm; an axle, having an axis, attached to the object body; and an axle support attached to the substrate and having a support surface. The axle has a rounded cross-section, as manufactured and forms a non-zero angle with a perpendicular to the surface. The object is capable of rotating about the axle.

Abstract: The present invention concerns an electrical junction between one transistor and at least one voltage sensitive cell such as a neuron. The invention further concerns transistors to be used in said junction and methods for their preparation. By another aspect the invention concerns “an artificial chemical synapse” i.e. a junction between a cell, which secretes an agent, and a transistor bearing receptors for the agent, wherein binding of the agent to the receptor changes an electrical property off the transistor.

Abstract: The present invention concerns an electrical junction between one transistor and at least one voltage sensitive cell such as a neuron. The invention further concerns transistors to be used in said junction and methods for their preparation. By another aspect the invention concerns “an artificial chemical synapse” i.e. a junction between a cell, which secretes an agent, and a transistor bearing receptors for the agent, wherein binding of the agent to the receptor changes an electrical property off the transistor.

Abstract: An improved density semiconductor device having a novel buried interconnect is described. The buried interconnect electrically connects electrical device regions on a semiconductor substrate such that other structures may directly overlie the buried interconnect but not be electrically connected to the electrically conductive portions of the interconnect. The interconnect is composed of a buried conductor and conductive segments. The conductive segments are electrically joined to the buried conductor so as to form an electrical pathway. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. A nonconductive portion of selective poly-epi silicon is then formed over the buried conductor by oxidizing at least some of the selective poly-epi silicon layer.

Abstract: An improved density semiconductor device having a buried interconnect is described. The buried interconnect incorporates an elevated source/drain structure formed by selective poly-epi silicon growth and silicidized source/drain/gate interconnect segments. First, a buried conductor is formed over an oxidized portion of a first field oxide. A layer of selective poly-epi silicon is then grown over the surface of the substrate. At least some of the selective poly-epi silicon layer is then oxidized. A layer of refractory metal is then deposited, annealed, and etched to complete the buried interconnect.

Abstract: A high-quality, highly reliable, composite dielectric layer for a semiconductor device. The composite dielectric layer is formed by nitriding a silicon surface, forming an oxide layer on the nitrided silicon surface, and then annealing the nitrided-silicon surface and the oxide in an oxygen ambient.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradition of the current-voltage characteristics of the device.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradation of the current-voltage characteristics of the device.

Abstract: A process for fabricating an MOS electrically programmable memory array which includes a plurality of floating gate memory devices is disclosed. The process employs two layers of polysilicon, each of which are used to define a plurality of spaced-apart parallel lines with the lines of the other layer. Doped bit line regions are formed in the substrate in alignment with the first lines prior to the fabrication of the second lines. The first lines are etched in alignment with the second lines to define floating gates. Overlying metal lines (bit lines) are formed over the doped regions and coupled to the doped regions through periodic contacts. Substantially fewer contacts are required than in prior art arrays, permitting the fabrication of a higher density array.

Abstract: A high density, read-only, mask programmed memory and memory cell fabricated with two layers of polycrystalline silicon (polysilicon) is disclosed. Elongated doped substrate regions form source/drain regions for the cells and are used as bit lines for the memory. The first layer of polysilicon defines gates for the cells; the second layer of polysilicon defines transverse work lines. Programming consists of selective contacts between the first and second layers of polysilicon over the active regions of the cells. A cell area of approximately 0.125 mils.sup.2 is realized.

Abstract: A semiconductor device having at least an insulated gate field effect transistor. According to the invention, the device comprises a first semiconductor region of a first conductivity type, an inset insulating pattern in a surface of said semiconductor region, a second region of the second conductivity type surrounded by said pattern, and source and drain zones of the first conductivity type which adjoin the insulating pattern. Said field effect transistor is preferably combined with a complementary field effect transistor provided beside it in the first region. The invention also comprises a very advantageous method of manufacturing said structure in which the insulating pattern and the gate electrodes serve as masks.

Abstract: A semiconductor device particularly suitable for ICs with complementary field effect transistors and/or bipolar circuit elements comprises a semiconductor body having a first type substrate region on which is a second type epitaxial layer of which a part is bounded by an inset insulating pattern. A first type zone adjoins the inset pattern and extends down to the substrate region. Source and drain zones of an IGFET adjoin the pattern and are provided in the said epitaxial part, and a further circuit element is provided in the said first type zone.