Patents by Inventor Joseph Shepard
Joseph Shepard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230170661Abstract: Described is a directed energy system that has a compact and modular configuration and that enables movement/assembly by a two-user team. The directed energy system includes one or more high-power laser sources that house one or more high-power fiber amplifiers, a beam combiner optically coupled to the one or more high-power laser sources, a beam director coupled to the beam combiner, a command and control module configurable to control operation of the one or more high-power fiber amplifiers. The directed energy system also includes a handheld controller with an integrated monitor, the handheld controller configurable to send control signals to the handheld controller module to control operation of the handheld controller module and a power module that includes batteries and power converters that provide electrical power required to run the directed energy system.Type: ApplicationFiled: August 2, 2021Publication date: June 1, 2023Inventors: Jennifer Riley, Edward Merryman, Joseph Shepard
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Publication number: 20190019862Abstract: Methods for preventing fin bending in FinFET devices and related devices are provided. Embodiments include forming fins in a substrate; forming a non-conformal sacrificial layer over and between the fins to structurally conjoin the fins or an array of fins for structural integrity; forming a first gap-fill dielectric over the sacrificial layer and fins; recessing the first gap-fill dielectric to expose an upper portion of the fins and sacrificial layer; etching the sacrificial layer to expose the fins; forming a second gap-fill dielectric over the first gap-fill dielectric and over and between the fins; and recessing the second gap-fill dielectric to expose the upper portion of the fins.Type: ApplicationFiled: July 13, 2017Publication date: January 17, 2019Inventors: A K M Zahidur Rahim CHOWDHURY, Shahrukh Akbar KHAN, Joseph SHEPARD, JR., Mohammad HASANUZZAMAN, Naved A. SIDDIQUI, Shafaat AHMED
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Publication number: 20070128859Abstract: A stepper is combined with hardware that deposits a layer of material in the course of forming an integrated circuit, thus performing the deposition, patterning and cleaning without exposing the wafer to a transfer between tools and combining the function of three tools in a composite tool. The pattern-defining material is removed by the application of UV light through the mask of the stepper, thereby eliminating the bake and development steps of the prior art method. Similarly, a flood exposure of UV eliminates the cleaning steps of the prior art method.Type: ApplicationFiled: December 1, 2005Publication date: June 7, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Chudzik, Joseph Shepard
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Publication number: 20070111430Abstract: A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.Type: ApplicationFiled: January 3, 2007Publication date: May 17, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael CHUDZIK, Louis HSU, Joseph SHEPARD, William TONTI
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Publication number: 20070064395Abstract: A cooling system for a semiconductor substrate includes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.Type: ApplicationFiled: November 9, 2006Publication date: March 22, 2007Inventors: Howard Chen, Louis Hsu, Joseph Shepard
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Publication number: 20060289903Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: ApplicationFiled: August 30, 2006Publication date: December 28, 2006Inventors: Wanda Andreoni, Alessandro Callegari, Eduard Cartier, Alessandro Curioni, Christopher D'Emic, Evgeni Gousev, Michael Gribelyuk, Paul Jamison, Rajarao Jammy, Dianne Lacey, Fenton McFeely, Vijay Narayanan, Carlo Pignedoli, Joseph Shepard, Sufi Zafar
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Publication number: 20060099815Abstract: A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.Type: ApplicationFiled: December 23, 2005Publication date: May 11, 2006Inventors: Howard Chen, Louis Hsu, Joseph Shepard
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Publication number: 20060035393Abstract: The invention provides methods for determining film continuity and growth modes in thin dielectric films. The continuity determining method comprises: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison.Type: ApplicationFiled: August 13, 2004Publication date: February 16, 2006Applicant: International Business Machines CorporationInventors: Michael Chudzik, Joseph Shepard
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Publication number: 20050280105Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: ApplicationFiled: June 22, 2004Publication date: December 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wanda Andreoni, Alessandro Callegari, Eduard Cartier, Alessandro Curioni, Christopher D'Emic, Evengi Gousev, Michael Gribelyuk, Paul Jamison, Rajarao Jammy, Dianne Lacey, Fenton McFeely, Vijay Narayanan, Carlo Pignedoli, Joseph Shepard, Sufi Zafar
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Publication number: 20050266652Abstract: A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.Type: ApplicationFiled: May 27, 2004Publication date: December 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Chudzik, Louis Hsu, Joseph Shepard, William Tonti
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Patent number: 6930060Abstract: Methods for preparing a silicon oxynitride layer where the silicon oxynitride layer is deposited atop a substrate and have a low concentration of nitrogen at the interface of the silicon oxynitride layer and the substrate. The silicon oxynitride layer is formed by pulsing at least one interface precursor onto a substrate, where said substrate chemisorbs a portion of said at least one interface precursor to form a monolayer of said at least one interface precursor; and pulsing a nitrogen-containing precursor onto said substrate containing said monolayer of interface precursor, where said monolayer of said at least one interface precursor chemisorbs a portion of said nitrogen-containing precursor to form a monolayer of said nitrogen-containing precursor. The interface precursor includes oxygen-containing or silicon-containing precursor gasses.Type: GrantFiled: June 18, 2003Date of Patent: August 16, 2005Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Michael P. Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul D. Kirsch, Kristen C. Scheer, Joseph Shepard, Jr.
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Publication number: 20050059238Abstract: A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.Type: ApplicationFiled: September 12, 2003Publication date: March 17, 2005Applicant: International Business Machines CorporationInventors: Howard Chen, Louis Hsu, Joseph Shepard
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Publication number: 20050023664Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.Type: ApplicationFiled: August 31, 2004Publication date: February 3, 2005Inventors: Michael Chudzik, Robert Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph Shepard, Anna Wanda Topol
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Publication number: 20040256664Abstract: Methods for preparing a silicon oxynitride layer where the silicon oxynitride layer is deposited atop a substrate and have a low concentration of nitrogen at the interface of the silicon oxynitride layer and the substrate. The silicon oxynitride layer is formed by pulsing at least one interface precursor onto a substrate, where said substrate chemisorbs a portion of said at least one interface precursor to form a monolayer of said at least one interface precursor; and pulsing a nitrogen-containing precursor onto said substrate containing said monolayer of interface precursor, where said monolayer of said at least one interface precursor chemisorbs a portion of said nitrogen-containing precursor to form a monolayer of said nitrogen-containing precursor. The interface precursor includes oxygen-containing or silicon-containing precursor gasses.Type: ApplicationFiled: June 18, 2003Publication date: December 23, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Michael P. Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul D. Kirsch, Kristen C. Scheer, Joseph Shepard
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Patent number: D803116Type: GrantFiled: October 29, 2014Date of Patent: November 21, 2017Inventors: Jeremiah Joseph Shepard, Przemyslaw A. Zagrodzki, Angela L. Petroski, Marc Andrew Yesnik