Patents by Inventor Joseph Shinnerl

Joseph Shinnerl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060190889
    Abstract: Placement or floorplanning of an integrated circuit is performed by constructing legal layouts at every level of a hierarchy of subsets of modules representing the integrated circuit, by scalably incorporating legalization into each level of the hierarchy, so that satisfiability of constraints is explicitly enforced at every level, in order to eliminate backtracking and post-hoc legalization.
    Type: Application
    Filed: January 16, 2006
    Publication date: August 24, 2006
    Inventors: Jingsheng Cong, Michail Romesis, Joseph Shinnerl