Patents by Inventor Joseph Shor
Joseph Shor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11985260Abstract: A method for creating a physical unclonable function (PUF) bit for use with transistor circuitry includes performing a tilt test on a PUF cell of a transistor circuitry, comprising tilting the PUF cell at least once, and comparing a mismatch of a response of the PUF cell to a tilt threshold. A magnitude of the mismatch is determined. A mismatch magnitude below the tilt threshold is considered a first logic value” and a mismatch magnitude above the tilt threshold is considered a second logic value. The mismatch magnitude of the PUF cell is random. The absolute value of the mismatch magnitude is used as an entropy source to produce at least one PUF bit called a mirror PUF bit.Type: GrantFiled: October 20, 2021Date of Patent: May 14, 2024Inventors: Yitzhak Schifmann, Joseph Shor
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Publication number: 20240053386Abstract: A method for measuring voltage droop and temperature in a circuit include using capacitive coupling to couple a bias voltage of a current controlled oscillator (CCO) to a noisy digital Vcc (VCCD) supply, so that a frequency of the CCO is independent of a DC Vcc level of the noisy VCCD supply and the CCO measures an AC voltage droop of the noisy VCCD supply and a temperature which is dependent upon the AC voltage droop.Type: ApplicationFiled: July 31, 2023Publication date: February 15, 2024Applicant: Bar Ilan UniversityInventors: Joseph Shor, Amir Mizrahi, Gil Golan, Orel Dahaman, Omer Nechushtan
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Publication number: 20220166431Abstract: A technique to mitigate timing errors induced by power supply droops includes an inverter-based droop detector as well as Dual Mode Logic (DML) to achieve a droop-resist ant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to Process/Voltage/Temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved.Type: ApplicationFiled: November 18, 2021Publication date: May 26, 2022Applicant: Bar Ilan UniversityInventors: Joseph Shor, Yitzhak Schifmann, Inbal Stanger, Netanel Shavit, Edison Ramiro Taco Lasso, Alexander Fish
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Publication number: 20220131713Abstract: A method for creating a physical unclonable function (PUF) bit for use with transistor circuitry includes performing a tilt test on a PUF cell of a transistor circuitry, comprising tilting the PUF cell at least once, and comparing a mismatch of a response of the PUF cell to a tilt threshold. A magnitude of the mismatch is determined. A mismatch magnitude below the tilt threshold is considered a first logic value” and a mismatch magnitude above the tilt threshold is considered a second logic value. The mismatch magnitude of the PUF cell is random. The absolute value of the mismatch magnitude is used as an entropy source to produce at least one PUF bit called a mirror PUF bit.Type: ApplicationFiled: October 20, 2021Publication date: April 28, 2022Applicant: Birad - Research & Development Company Ltd.Inventors: Yitzhak Schifmann, Joseph Shor
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Patent number: 11112816Abstract: A sensor circuit includes a bandgap reference circuit (BGREF) that produces two outputs, a temperature dependent output and a reference voltage, which does not change with temperature. The temperature dependent output includes a PTAT (proportional to absolute temperature, rising with increased temperature) portion and a CTAT (complementary to absolute temperature, falling with increased temperature) portion. Circuitry is provided that calculates the reference voltage by adding the PTAT portion and a divided version of the CTAT portion in which the CTAT portion has been divided by a divisor.Type: GrantFiled: April 22, 2018Date of Patent: September 7, 2021Assignee: Birad—Research & Development Company Ltd.Inventors: Ori Bass, Joseph Shor
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Patent number: 11114352Abstract: A process monitor circuitry is described that can measure the electron mobility (?), oxide capacitance (Cox) and threshold voltage (Vth) of an integrated circuit.Type: GrantFiled: August 25, 2019Date of Patent: September 7, 2021Assignee: Birad—Research & Development Company Ltd.Inventors: Joseph Shor, Liron Lisha
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Patent number: 10998889Abstract: A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.Type: GrantFiled: December 22, 2017Date of Patent: May 4, 2021Assignee: Birad-Research & Development Company Ltd.Inventors: Joseph Shor, Natan Vinshtok-Melnik
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Patent number: 10999083Abstract: A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.Type: GrantFiled: November 20, 2019Date of Patent: May 4, 2021Assignee: Birad—Research & Development Corapany Ltd.Inventors: Joseph Shor, Yoav Weizman, Yitzhak Schifmann
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Publication number: 20210057294Abstract: A process monitor circuitry is described that can measure the electron mobility (?), oxide capacitance (Cox) and threshold voltage (Vth) of an integrated circuit.Type: ApplicationFiled: August 25, 2019Publication date: February 25, 2021Applicant: Birad - Research & Development Company Ltd.Inventors: Joseph Shor, Liron Lisha
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Patent number: 10871404Abstract: A thermal sensor includes a first resistor and a first capacitor. The first resistor is a thermistor. A first current source is coupled to the first resistor and the first capacitor. The first current source alternately charges the first resistor and the first capacitor each to a reference voltage, Vtherm. An output of the thermal sensor is a function of a resistance-capacitance (RC) time constant of the first resistor and the first capacitor.Type: GrantFiled: May 16, 2018Date of Patent: December 22, 2020Assignee: Birad—Research & Development Company Ltd.Inventors: Anatoli Mordakhay, Joseph Shor
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Patent number: 10852756Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.Type: GrantFiled: June 18, 2018Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Kosta Luria, Alexander Lyakhov, Joseph Shor, Michael Zelikson
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Patent number: 10848327Abstract: A method for detecting unreliable bits in transistor circuitry includes adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit. The adjusting includes tilting the PUF cell to either a zero or one state: if the PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable.Type: GrantFiled: June 28, 2018Date of Patent: November 24, 2020Assignee: Birad—Research & Development Company Ltd.Inventors: Yitzhak Shifman, Avi Miller, Joseph Shor
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Patent number: 10630493Abstract: A physical unclonable function (PUF) array includes a plurality of PUF transistor cells each of which includes at least one inverter. An input and an output of the at least one inverter are shorted to a first reference node. There is adjustment circuitry for adjusting a reference voltage of the first reference node, and measurement circuitry for measuring a trip point of the at least one inverter. If the trip point is close to the reference voltage then bits of the at least one inverter are defined as unstable.Type: GrantFiled: November 29, 2017Date of Patent: April 21, 2020Assignee: Birad—Research & Development Company Ltd.Inventors: Joseph Shor, Roi Levi, Yoav Weizman
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Publication number: 20200092117Abstract: A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.Type: ApplicationFiled: November 20, 2019Publication date: March 19, 2020Applicant: Birad - Research & Development Company Ltd.Inventors: Joseph Shor, Yoav Weizman, Yitzhak Schifmann
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Publication number: 20200007350Abstract: A method for detecting unreliable bits in transistor circuitry includes adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit. The adjusting includes tilting the PUF cell to either a zero or one state: if the PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Applicant: Birad - Research & Development Company Ltd.Inventors: Yitzhak Shifman, Avi Miller, Joseph Shor
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Publication number: 20190353534Abstract: A thermal sensor includes a first resistor and a first capacitor. The first resistor is a thermistor. A first current source is coupled to the first resistor and the first capacitor. The first current source alternately charges the first resistor and the first capacitor each to a reference voltage, Vtherm. An output of the thermal sensor is a function of a resistance-capacitance (RC) time constant of the first resistor and the first capacitor.Type: ApplicationFiled: May 16, 2018Publication date: November 21, 2019Applicant: Birad - Research & Development Company Ltd.Inventors: Anatoli Mordakhay, Joseph Shor
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Publication number: 20190324490Abstract: A sensor circuit includes a bandgap reference circuit (BGREF) that produces two outputs, a temperature dependent output and a reference voltage, which does not change with temperature. The temperature dependent output includes a PTAT (proportional to absolute temperature, rising with increased temperature) portion and a CTAT (complementary to absolute temperature, falling with increased temperature) portion. Circuitry is provided that calculates the reference voltage by adding the PTAT portion and a divided version of the CTAT portion in which the CTAT portion has been divided by a divisor.Type: ApplicationFiled: April 22, 2018Publication date: October 24, 2019Applicant: Birad - Research & Development Company Ltd.Inventors: Ori Bass, Joseph Shor
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Publication number: 20190199329Abstract: A sensor circuit includes at least one ring oscillator having a supply port supplied by at least one current source and a reference frequency. A comparator compares a frequency output of the at least one ring oscillator with the reference frequency to yield a measurement, such as a temperature measurement.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Applicant: Bar Ilan UniversityInventors: Joseph Shor, Natan Vinshtok-Melnik
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Publication number: 20190165953Abstract: A physical unclonable function (PUF) array includes a plurality of PUF transistor cells each of which includes at least one inverter. An input and an output of the at least one inverter are shorted to a first reference node. There is adjustment circuitry for adjusting a reference voltage of the first reference node, and measurement circuitry for measuring a trip point of the at least one inverter. If the trip point is close to the reference voltage then bits of the at least one inverter are defined as unstable.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Applicant: Bar Ilan UniversityInventors: Joseph Shor, Roi Levi, Yoav Weizman
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Publication number: 20190074984Abstract: A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.Type: ApplicationFiled: September 3, 2017Publication date: March 7, 2019Applicant: BAR-ILAN UNIVERSITYInventors: Joseph Shor, Yoav Weizman, Yitzhak Schifmann