Patents by Inventor Joseph Skazinski

Joseph Skazinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230069222
    Abstract: A method for translating data from one application programming format to another programming format is provided. The method includes receiving a request to provide data in a second application programming format from data in a first application programming format, retrieving an interpretation data object associated with the request and the second application programming format, the interpretation data object including data representing source data entities in the first application programming format and target data entities in the second application programming format, performing a function identified in the interpretation data object, the function performed on a value of the source data entities to yield a value of target data entities based on an association included in the interpretation data object between the function, the source data entities, and the target data entities, and providing the data in the second application programming format based on the value of the target data entities.
    Type: Application
    Filed: August 12, 2021
    Publication date: March 2, 2023
    Inventor: Joseph SKAZINSKI
  • Patent number: 11403218
    Abstract: A system includes first and second redundant controllers, and at least one logical volume accessible to the first and second redundant controllers. The system also includes metadata fields associated with the at least one logical volume. The metadata fields include a first age field configured to store a first age value associated with the first controller and a second age field configured to store a second age value associated with the second controller. The first age value and the second age value are employed to provide an indication of whether cache data for the at least one logical volume is valid. The system further includes a processor configured to update the first and second age values in the respective first and second age fields.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 2, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ritvik Viswanatha, Kishan Gelli, Joseph Skazinski
  • Publication number: 20220147451
    Abstract: A system includes first and second redundant controllers, and at least one logical volume accessible to the first and second redundant controllers. The system also includes metadata fields associated with the at least one logical volume. The metadata fields include a first age field configured to store a first age value associated with the first controller and a second age field configured to store a second age value associated with the second controller. The first age value and the second age value are employed to provide an indication of whether cache data for the at least one logical volume is valid. The system further includes a processor configured to update the first and second age values in the respective first and second age fields.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Inventors: Ritvik Viswanatha, Kishan Gelli, Joseph Skazinski
  • Publication number: 20060069960
    Abstract: A system and method for testing input and output paths connected to an embedded processor. Specialized test software operating on the embedded processor creates one or more test workers or threads, each having a specific routine to perform, which are executed in parallel, stressing various communication paths. The results may be analyzed to help in many different ways during the life cycle of the device with the embedded controller.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 30, 2006
    Applicant: KOZIO, INC.
    Inventors: Keith Short, Joseph Skazinski
  • Publication number: 20050120340
    Abstract: The apparatus includes an input module for receiving hardware description data. The hardware description data describes hardware components of an embedded system. The apparatus also includes a build module for generating a board support layer for interfacing with the hardware components. The system may include the apparatus, an automation server coupled to a communications network, and a graphical user interface configured to display selectable icons representative of hardware elements from a plurality of hardware element icons, organize the selected icons into a hardware design, and generate hardware description data from the hardware design. The method includes receiving hardware description data describing hardware components of an embedded system, generating an embedded system board support layer in response to the described hardware description data for interfacing with the hardware components, and compiling the embedded system board support layer into executable code.
    Type: Application
    Filed: September 9, 2004
    Publication date: June 2, 2005
    Inventors: Joseph Skazinski, Keith Short
  • Patent number: 6247099
    Abstract: System, method and computer program for maintaining cache coherency amongst a plurality of caching storage controllers operating in unison supplying data in response to requests from one or more host computers. The method comprises the steps of defining a reservation data structure to maintain reserved, partial, and full ownership status of data extents that are part of the logical unit or storage volume, and using the reservation data structure to verify that a new update to the data is allowed.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: June 12, 2001
    Assignee: International Business Machines Corporation
    Inventors: Joseph Skazinski, Brian McKean, Noel S. Otterness