Patents by Inventor Joseph Smart

Joseph Smart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150279945
    Abstract: Methods for manufacturing semiconductor wafer structures are described which exhibit improved lifetime and reliability. The methods comprise transferring an active semiconductor layer structure from a native non-lattice-matched semiconductor growth substrate to a working substrate, wherein strain-matching layers, and optionally a portion of the active semiconductor layer structure, are removed. In certain embodiment, the process of attaching the active semiconductor layer structure to the working substrate includes annealing at an elevated temperature for a specified time.
    Type: Application
    Filed: October 25, 2013
    Publication date: October 1, 2015
    Inventors: Daniel Francis, Dubravko Babic, Firooz Nasser-Faili, Felix Ejeckham, Quentin Diduck, Joseph Smart, Kristopher Matthews, Frank Lowe
  • Patent number: 7968391
    Abstract: A high voltage and high power gallium nitride (GaN) transistor structure is disclosed. A plurality of structural epitaxial layers including a GaN buffer layer is deposited on a substrate. A GaN termination layer is deposited on the plurality of structural epitaxial layers. The GaN termination layer is adapted to protect the plurality of structural epitaxial layers from surface reactions. The GaN termination layer is sufficiently thin to allow electrons to tunnel through the GaN termination layer. Electrical contacts are deposited on the GaN termination layer, thereby forming a high electron mobility transistor.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: June 28, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey B. Shealy
  • Patent number: 7459356
    Abstract: The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: December 2, 2008
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey Shealy
  • Patent number: 7408182
    Abstract: The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: August 5, 2008
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, David Grider, Shawn Gibb, Brook Hosse, Jeffrey Shealy
  • Publication number: 20070101932
    Abstract: Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm?2 or less and high-quality AlN substrates having surfaces of any desired crystallographic orientation fabricated from these bulk crystals.
    Type: Application
    Filed: May 9, 2006
    Publication date: May 10, 2007
    Applicant: Crystal IS, Inc.
    Inventors: Leo Schowalter, Glen Slack, J. Rojo, Robert Bondokov, Kenneth Morgan, Joseph Smart
  • Publication number: 20060199364
    Abstract: A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 7, 2006
    Inventors: James Shealy, Joseph Smart
  • Patent number: 7052942
    Abstract: The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: May 30, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, David Grider, Shawn Gibb, Brook Hosse, Jeffrey Shealy
  • Patent number: 7033961
    Abstract: The present invention relates to an epitaxial structure having one or more structural epitaxial layers, including a gallium nitride (GaN) layer, which is deposited on a substrate, and a method of growing the epitaxial structure, wherein the structural epitaxial layers can be separated from the substrate. In general, a sacrificial epitaxial layer is deposited on the substrate between the substrate and the structural epitaxial layers, and the structural epitaxial layers are deposited on the sacrificial layer. After growth, the structural epitaxial layers are separated from the substrate by oxidizing the sacrificial layer. The structural epitaxial layers include a nucleation layer deposited on the sacrificial layer and a gallium nitride layer deposited on the nucleation layer. Optionally, the oxidation of the sacrificial layer may also oxidize the nucleation layer.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: April 25, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey B. Shealy
  • Patent number: 7026665
    Abstract: The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: April 11, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, Brook Hosse, Shawn Gibb, David Grider, Jeffrey Shealy