Abstract: Embodiments of a method and an apparatus for a quadrature hybrid are disclosed. In an embodiment, a quadrature hybrid includes a first port, a second port, a third port, a fourth port, first, second, and third inductors, first, second, third, and fourth capacitors, and a first variable capacitor tuning network connected between the first port and the fourth port, and a second variable capacitor tuning network connected between the second port and the third port.

Abstract: an amplifier having an input terminal and an output terminal. The input terminal is configured to receive a radio frequency (RF) input signal. The device includes an output network coupled to the output terminal of the power amplifier and a first passively tunable integrated circuit (PTIC) coupled to the output network. The first PTIC includes a direct-current (DC) bias voltage input terminal configured to receive a fixed bias voltage, a control signal input terminal configured to receive a time-varying control signal, wherein the fixed bias voltage in combination with the time-varying control signal sets an operating reference point of the first PTIC, and an input terminal electrically connected to the output terminal of the amplifier, wherein a change in an output voltage signal generated by the power amplifier causes the first PTIC to modify a first effective impedance of a load presented to the power amplifier via the output network.

Abstract: Embodiments of a method and an apparatus for a quadrature hybrid are disclosed. In an embodiment, a quadrature hybrid includes a first port, a second port, a third port, a fourth port, first, second, and third inductors, first, second, third, and fourth capacitors, and a first variable capacitor tuning network connected between the first port and the fourth port, and a second variable capacitor tuning network connected between the second port and the third port.

Abstract: A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

Abstract: Aspects of the subject disclosure may include a Doherty amplifier that includes a carrier amplifier having an output terminal, an output network coupled to the output terminal, and a peaking amplifier, wherein the output network comprises a non-linear reactance component, and wherein the non-linear reactance component changes an effective impedance of a load presented to the carrier amplifier when the peaking amplifier is off. Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include a Doherty amplifier that includes a carrier amplifier having an output terminal, an output network coupled to the output terminal, and a peaking amplifier, wherein the output network comprises a non-linear reactance component, and wherein the non-linear reactance component changes an effective impedance of a load presented to the carrier amplifier when the peaking amplifier is off. Other embodiments are disclosed.

Abstract: Embodiments of a temperature compensation circuit and a temperature compensated amplifier circuit are disclosed. In an embodiment, a temperature compensation circuit includes a bias reference circuit having serially connected transistor devices and a driver transistor device connected to the bias reference circuit. At least one of the serially connected transistor devices includes a resistor connected between two terminals of the at least one of the serially connected transistor devices. The driver transistor device is configured to generate a drive current based on a resistance value of the resistor.

Abstract: A circulator-coupler device includes a ferrite element, a resonator over and aligned along an axis with the ferrite element, and a plurality of resonator ports connected to the resonator. The plurality of resonator ports includes first and second resonator ports, and a first portion of a perimeter of the resonator extends between the first and second resonator ports. The circulator further includes a coupler element positioned across a gap from the first portion of the perimeter of the resonator, and a coupler port connected to the coupler element. The device also may include a permanent magnet aligned along the axis with the ferrite element, where the permanent magnet biases the ferrite element and causes a signal conducted through the resonator to have a directionality along a rotational direction that extends from the first resonator port to the second resonator port.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and further includes a first amplifier die, a second amplifier die, and a third amplifier die on the mounting surface. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path, the second amplifier die is configured to amplify a second RF signal along a second signal path, and the third amplifier die is configured to amplify a third RF signal along a third signal path. A side of the first amplifier die including a first output terminal faces a side of the second amplifier die including a second output terminal. The second signal path is parallel to the first signal path, and the third signal path is orthogonal to the first and second signal paths.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and further includes a first amplifier die, a second amplifier die, and a third amplifier die on the mounting surface. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path, the second amplifier die is configured to amplify a second RF signal along a second signal path, and the third amplifier die is configured to amplify a third RF signal along a third signal path. A side of the first amplifier die including a first output terminal faces a side of the second amplifier die including a second output terminal. The second signal path is parallel to the first signal path, and the third signal path is orthogonal to the first and second signal paths.

Abstract: Embodiments of a temperature compensation circuit and a temperature compensated amplifier circuit are disclosed. In an embodiment, a temperature compensation circuit includes a bias reference circuit having serially connected transistor devices and a driver transistor device connected to the bias reference circuit. At least one of the serially connected transistor devices includes a resistor connected between two terminals of the at least one of the serially connected transistor devices. The driver transistor device is configured to generate a drive current based on a resistance value of the resistor.

Abstract: Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that enables fast switching between an on state bias voltage and an off state bias voltage for the power amplifier. The bias controller can transition a low impedance switch to an on state to electrically couple a first electrode of a charge holding capacitor to an input of the power amplifier. The charge holding capacitor can be pre charged with the on state bias voltage to quickly provide the on state bias voltage to the power amplifier. The bias controller can also transition the low impedance switch to an off state to couple the input of the power amplifier to the off state bias voltage.

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that automatically sets a bias voltage of a power amplifier device by monitoring a reference device that is in a scaled relationship with the power amplifier device, and integrally is formed with the power amplifier device on a same semiconductor die. The bias controller can compare a voltage at an input to the reference device to a reference voltage, and then adjust a voltage at a control input of the reference device to a stabilized voltage that induces the reference device to drive the voltage at the input to the reference device equal to the reference voltage. Finally, the bias controller can transform, based on the scaled relationship, the stabilized voltage into a bias voltage applied to a control input of the power amplifier device.

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that enables fast switching between an on state bias voltage and an off state bias voltage for the power amplifier. The bias controller can transition a low impedance switch to an on state to electrically couple a first electrode of a charge holding capacitor to an input of the power amplifier. The charge holding capacitor can be pre charged with the on state bias voltage to quickly provide the on state bias voltage to the power amplifier. The bias controller can also transition the low impedance switch to an off state to couple the input of the power amplifier to the off state bias voltage.

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that automatically sets a bias voltage of a power amplifier device by monitoring a reference device that is in a scaled relationship with the power amplifier device, and integrally is formed with the power amplifier device on a same semiconductor die. The bias controller can compare a voltage at an input to the reference device to a reference voltage, and then adjust a voltage at a control input of the reference device to a stabilized voltage that induces the reference device to drive the voltage at the input to the reference device equal to the reference voltage. Finally, the bias controller can transform, based on the scaled relationship, the stabilized voltage into a bias voltage applied to a control input of the power amplifier device.

Abstract: An amplifier device includes an input terminal, an output terminal, a first transistor having a control terminal and first and second current-carrying terminals, and a class-J circuit coupled between the second current-carrying terminal of the first transistor and the output terminal and configured to harmonically terminate the first transistor. The class-J circuit may include a first resonator, characterized by a first resonant frequency substantially equal to a second harmonic frequency. The first resonator may be coupled between the second current-carrying terminal and a voltage reference. A shunt inductor that is distinct from the first resonator may be coupled between the second current-carrying terminal and the voltage reference.

Abstract: Hybrid power amplifier circuits, modules, or systems, and methods of operating same, are disclosed herein. In one example embodiment, a hybrid power amplifier circuit includes a preliminary stage amplification device, a final stage amplification device, and intermediate circuitry at least indirectly coupling the preliminary stage amplification device and the final stage amplification device. The intermediate circuitry includes a low-pass circuit and a high-pass circuit, and the hybrid power amplifier circuit is configured to amplify a first signal component at a fundamental frequency. Due at least in part to the intermediate circuitry, a phase of a second signal component at a harmonic frequency that is a multiple of the fundamental frequency is shifted.

Abstract: Hybrid power amplifier circuits, modules, or systems, and methods of operating same, are disclosed herein. In one example embodiment, a hybrid power amplifier circuit includes a preliminary stage amplification device, a final stage amplification device, and intermediate circuitry at least indirectly coupling the preliminary stage amplification device and the final stage amplification device. The intermediate circuitry includes a low-pass circuit and a high-pass circuit, and the hybrid power amplifier circuit is configured to amplify a first signal component at a fundamental frequency. Due at least in part to the intermediate circuitry, a phase of a second signal component at a harmonic frequency that is a multiple of the fundamental frequency is shifted.

Abstract: A reference circuit includes an integrated circuit (IC) formed on a semiconductor substrate including a first spiral inductor and a second spiral inductor. The first spiral inductor is formed from a first metal layer over the substrate. The second spiral inductor is formed from a second metal layer. The second spiral inductor is offset from the first spiral inductor and includes a first portion overlapping the first spiral inductor. A first capacitor includes a first terminal coupled to receive a radio frequency (RF) signal and a second terminal coupled to a first terminal of the first spiral inductor, and second capacitor includes a first terminal coupled to a second terminal of the first spiral inductor.