Patents by Inventor Joseph Steigerwald
Joseph Steigerwald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955534Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: December 7, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Publication number: 20240047556Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Publication number: 20230387121Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Joseph STEIGERWALD, Tahir GHANI, Oleg GOLONZKA
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Patent number: 11776959Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.Type: GrantFiled: October 28, 2020Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Joseph Steigerwald, Tahir Ghani, Oleg Golonzka
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Publication number: 20230101723Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Patent number: 11581419Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: October 26, 2020Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Patent number: 11476334Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.Type: GrantFiled: February 8, 2018Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Orb Acton, Joseph Steigerwald, Anand Murthy, Scott Maddox, Jenny Hu
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Publication number: 20210066475Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: October 26, 2020Publication date: March 4, 2021Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Publication number: 20210043627Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Inventors: Joseph STEIGERWALD, Tahir GHANI, Oleg GOLONZKA
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Patent number: 10861851Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.Type: GrantFiled: November 30, 2017Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Joseph Steigerwald, Tahir Ghani, Oleg Golonzka
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Patent number: 10854731Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: August 9, 2019Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Publication number: 20200343343Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.Type: ApplicationFiled: February 8, 2018Publication date: October 29, 2020Applicant: Intel CorporationInventors: Orb Acton, Joseph Steigerwald, Anand Murthy, Scott Maddox, Jenny Hu
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Patent number: 10777655Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: December 30, 2017Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Publication number: 20200044049Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: August 9, 2019Publication date: February 6, 2020Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Publication number: 20190164897Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: December 30, 2017Publication date: May 30, 2019Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Publication number: 20180097003Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.Type: ApplicationFiled: November 30, 2017Publication date: April 5, 2018Inventors: Joseph Steigerwald, Tahir Ghani, Oleg Golonzka
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Patent number: 9876016Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.Type: GrantFiled: December 30, 2011Date of Patent: January 23, 2018Assignee: Intel CorporationInventors: Joseph Steigerwald, Tahir Ghani, Oleg Golonzka
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Publication number: 20160225715Abstract: A transistor contact of the present description may be fabricated by forming a via through an interlayer dielectric layer disposed on a microelectronic substrate, wherein the via extends from a first surface of the interlayer dielectric layer to the microelectronic substrate forming a via sidewall and exposing a portion of the microelectronic substrate. A conformal contact material layer may then be formed adjacent the exposed portion of the microelectronic substrate, the at least one via sidewall, and the interlayer dielectric first surface. An etch block plug formed within the via proximate the microelectronic substrate. The contact material layer not protected by the etch block plug may be removed followed by the removal of the etch block plug and the filling the via with a conductive material.Type: ApplicationFiled: November 20, 2013Publication date: August 4, 2016Applicant: INTEL CORPORATIONInventors: Anthony St. Amour, Joseph Steigerwald
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Publication number: 20140159159Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.Type: ApplicationFiled: December 30, 2011Publication date: June 12, 2014Inventors: Joseph Steigerwald, Tahir Ghani, Oleg Golonzka
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Publication number: 20060169409Abstract: An electropolish process may remove a conductive film from a semiconductor wafer. An electropolish apparatus having a pad over a platen may make surface-to-surface electrical contact with the conductive film of the wafer across the entire surface of the pad and the conductive film on the wafer. An electric field may be applied through openings in the pad and electrodes which receive potential by feedthroughs that extend through the platen to those electrodes. The electrodes in the feedthroughs may be electrically isolated from the pad and the platen. As a result, more uniform application of electrical potential across the surface to be polished may be achieved in some embodiments.Type: ApplicationFiled: March 29, 2006Publication date: August 3, 2006Inventor: Joseph Steigerwald