Patents by Inventor Joseph T. Kocis

Joseph T. Kocis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6800503
    Abstract: A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: October 5, 2004
    Assignee: International Business Machines Corporation
    Inventors: Joseph T. Kocis, James Tornello, Kevin S. Petrarca, Richard Volant, Seshadri Subbanna
  • Patent number: 6787427
    Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
  • Patent number: 6762667
    Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca, Kenneth J. Stein, William C. Wille
  • Publication number: 20040097003
    Abstract: A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer.
    Type: Application
    Filed: November 20, 2002
    Publication date: May 20, 2004
    Applicant: International Business Machines Corporation
    Inventors: Joseph T. Kocis, James Tornello, Kevin S. Petrarca, Richard Volant, Seshadri Subbanna
  • Publication number: 20040063293
    Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
    Type: Application
    Filed: October 1, 2003
    Publication date: April 1, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
  • Patent number: 6656809
    Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
  • Publication number: 20030210124
    Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.
    Type: Application
    Filed: June 19, 2003
    Publication date: November 13, 2003
    Inventors: Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca, Kenneth J. Stein, William C. Wille
  • Patent number: 6621392
    Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca, Kenneth J. Stein, William C. Wille
  • Publication number: 20030132453
    Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 17, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
  • Patent number: 6375859
    Abstract: A process for removing a resist material containing a chlorine residue from an organic substrate. The process first removes the chlorine residue from the resist material by exposing the resist material to an abbreviated plasma which also removes a portion of the resist material. The remainder of the resist material is removed by exposing the resist material to a solvent which does not affect the organic substrate.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: April 23, 2002
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, Joseph T. Kocis, Waldemar W. Kocon, Seshadri Subbanna