Patents by Inventor Joseph T. Lindgren
Joseph T. Lindgren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9054099Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.Type: GrantFiled: October 29, 2013Date of Patent: June 9, 2015Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Publication number: 20140054777Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.Type: ApplicationFiled: October 29, 2013Publication date: February 27, 2014Applicant: MICRON TECHNOLOGY, INC.Inventor: Joseph T. Lindgren
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Patent number: 8592254Abstract: Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.Type: GrantFiled: September 12, 2012Date of Patent: November 26, 2013Assignee: Micron Technology, Inc.Inventors: Joseph T. Lindgren, Warren M. Farnworth, William M. Hiatt, Nishant Sinha
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Patent number: 8569161Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.Type: GrantFiled: May 9, 2011Date of Patent: October 29, 2013Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Patent number: 8431484Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.Type: GrantFiled: April 4, 2011Date of Patent: April 30, 2013Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Publication number: 20130003303Abstract: Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Joseph T. Lindgren, Warren M. Farnworth, William M. Hiatt, Nishant Sinha
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Patent number: 8291966Abstract: Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.Type: GrantFiled: December 8, 2006Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Joseph T. Lindgren, Warren M. Farnworth, William M. Hiatt, Nishant Sinha
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Publication number: 20110212578Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.Type: ApplicationFiled: May 9, 2011Publication date: September 1, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Joseph T. Lindgren
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Publication number: 20110183514Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.Type: ApplicationFiled: April 4, 2011Publication date: July 28, 2011Inventor: Joseph T. Lindgren
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Patent number: 7939949Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.Type: GrantFiled: September 27, 2007Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Publication number: 20090085209Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Applicant: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Patent number: 7485565Abstract: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.Type: GrantFiled: August 17, 2006Date of Patent: February 3, 2009Assignee: Micron Technologies, Inc.Inventors: Jeffery N. Gleason, Joseph T. Lindgren
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Patent number: 7312164Abstract: A method for applying a passivation layer selectively on an exposed silicon surface includes use of a liquid phase solution supersaturated in silicon dioxide. The application is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated immersion time, and without subsequent heat treatment. In one embodiment, rapid coating of a wafer back side with silicon dioxide permits the use of a high-speed electroless process for plating the bond pad with a solder-enhancing material. In another embodiment, the walls of via holes and microvia holes in a silicon body may be passivated by applying the supersaturated solution prior to plugging the holes with conductive material.Type: GrantFiled: March 23, 2005Date of Patent: December 25, 2007Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Patent number: 7256115Abstract: A method and apparatus are disclosed for forming a tapered contact structure over a contact pad. The tapered contact structure may be used to securely anchor an overlying solder bump or solder ball. Additionally, the tapered contact structure allows the use of either larger contact pads or, alternately, allows a greater density of contact pads to be achieved on an integrated circuit substrate.Type: GrantFiled: August 31, 2004Date of Patent: August 14, 2007Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Joseph T. Lindgren
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Patent number: 7190052Abstract: A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures are exposed. The semiconductor device structure is formed by selectively forming the passivation layer on an exposed silicon-comprising surface by exposing surfaces of the semiconductor device to a liquid phase solution supersaturated in silicon dioxide. The exposure is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated time, and without subsequent heat treatment. A wafer that includes a back side coated with such a passivation layer may be subjected to a high-speed electroless process for plating the bond pad with a solder-enhancing material. The semiconductor device structure may also include via holes and microvia holes with walls that are passivated.Type: GrantFiled: June 3, 2003Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Patent number: 7186636Abstract: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.Type: GrantFiled: August 11, 2004Date of Patent: March 6, 2007Assignee: Micron Technology, Inc.Inventors: Jeffery N. Gleason, Joseph T. Lindgren
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Patent number: 7183133Abstract: Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.Type: GrantFiled: January 28, 2004Date of Patent: February 27, 2007Assignee: Micron Technology, Inc.Inventors: Joseph T. Lindgren, Warren M. Farnworth, William M. Hiatt, Nishant Sinha
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Patent number: 7067924Abstract: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.Type: GrantFiled: August 31, 2004Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Jeffery N. Gleason, Joseph T. Lindgren
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Patent number: 7052922Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.Type: GrantFiled: July 21, 2003Date of Patent: May 30, 2006Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren
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Patent number: 6905953Abstract: A method for applying a passivation layer selectively on an exposed silicon surface from a liquid phase solution supersaturated in silicon dioxide. The immersion is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated immersion time, and without subsequent heat treatment. In one embodiment, rapid coating of a wafer back side with silicon dioxide permits the use of a high-speed electroless process for plating the bond pad with a solder-enhancing material. In another embodiment, the walls of via holes and microvia holes in a silicon body may be passivated by immersion in the supersaturated solution prior to plugging the holes with conductive material.Type: GrantFiled: June 3, 2003Date of Patent: June 14, 2005Assignee: Micron Technology, Inc.Inventor: Joseph T. Lindgren