Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.

Abstract: A memory having a plurality of ferroelectric memory cells connected between first and second bit lines is disclosed. A read circuit is also connected between the first and second bit lines. A word select circuit selects one of the ferroelectric memory cells and generates a potential on the first hit line indicative of a value stored in the selected one of the plurality of ferroelectric memory cells. Each ferroelectric memory cell includes a ferroelectric capacitor and a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal. The ferroelectric capacitor is connected between the control terminal and the first switch terminal. First and second gates connect the ferroelectric memory cell to the bit lines in response to the word select circuit selecting that ferroelectric memory cell.

Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.

Abstract: A memory having a plurality of ferroelectric memory cells connected between first and second bit lines is disclosed. A read circuit is also connected between the first and second bit lines. A word select circuit selects one of the ferroelectric memory cells and generates a potential on the first hit line indicative of a value stored in the selected one of the plurality of ferroelectric memory cells. Each ferroelectric memory cell includes a ferroelectric capacitor and a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal. The ferroelectric capacitor is connected between the control terminal and the first switch terminal. First and second gates connect the ferroelectric memory cell to the bit lines in response to the word select circuit selecting that ferroelectric memory cell.

Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.

Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.

Abstract: A ferroelectric capacitor and method for making the same are disclosed. The ferroelectric capacitor may be constructed on a silicon substrate such as SiO2 or Si3N4. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode. The bottom electrode is constructed from a layer of platinum which is bonded to the silicon substrate by a layer of metallic oxide. The metallic oxide does not diffuse into the platinum; hence, a thinner layer of platinum may be utilized for the electrode. This reduces the vertical height of the capacitor and other problems associated with diffusion of the layer used to bond, the bottom electrode to the substrate surface.

Abstract: A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.