Abstract: An error detection and correction system for use in a data processing system wherein all single bit errors in a data word can be detected and corrected by the use of a unique modified Hamming code technique. In accordance therewith, during the write portion of a memory cycle, odd and even parity checks are made on a predetermined number of different, selected combinations of bits in each data word, to form a plurality of parity check bits which are combined with the original data word bits to form an extended data word. During the read portion of the memory cycle, the same number of odd and even parity checks are made on selected combinations of bits of the extended data word which combinations include the same selected combinations of bits used during the write portion plus the parity check bit associated therewith to provide a plurality of error bits.

Abstract: A system for automatically maintaining a record for an order of data priority of data stored in locations of an associative memory which compares the data stored in the locations with newly received data to generate a comparison output and where the order of priority is based on usage of data, comprising a read only memory a bit configuration reflecting an algorithm, connected from the associative memory for generating a first set of signals defining the least recently used location of the associative memory and for generating a second set of signals defining the order of word priority in terms of the associative memory locations, and a storage unit for receiving the second set of signals for subsequent feedback to the read only memory for re-defining the word priority as effected by newly received data.