Abstract: A direct memory access (DMA) controller, includes circuitry configured to load a DMA transfer descriptor configured to define which memory elements within a contiguous block of n memory elements are to be included in a given DMA transfer. The circuitry is further configured to, based on the DMA transfer descriptor, determine whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that two or more non-contiguous sub-blocks of memory elements within the contiguous block of n memory elements are to be transferred. The circuitry is further configured to, based on the determination of whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.

Abstract: A direct memory access (DMA) controller, includes circuitry configured to load a DMA transfer descriptor configured to define which memory elements within a contiguous block of n memory elements are to be included in a given DMA transfer. The circuitry is further configured to, based on the DMA transfer descriptor, determine whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that two or more non-contiguous sub-blocks of memory elements within the contiguous block of n memory elements are to be transferred. The circuitry is further configured to, based on the determination of whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.

Abstract: A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic.

Abstract: A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic.

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.

Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

Abstract: An instruction set is provided that features multiple instructions and various address modes to deliver a mixture of flexible microcontroller-like instructions and specialized digital signal processing (“DSP”) execute instructions from a single instruction stream. A subset of instructions of the instruction set can be executed by a processor. Similarly, another subset of the instructions can be utilized by the digital signal processor. A software application can thus take advantage of digital signal processing capabilities in the same program, obviating the need for separate programs for separate processors.

Abstract: A method, system and apparatus are providing fast access to memory in a stack. The system and apparatus include an address bit, a stack pointer, and fast access random access memory (“RAM”). The method provides that, when a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted in order to achieve an index of literal offset address mode.

Abstract: A method, system and apparatus are provided for alternating instruction sets in central processing units. A microcontroller is provided with a configuration mechanism, such as a fuse that, depending upon the setting, determines which of multiple instruction sets (or multiple parts of a single instruction set) can be processed by the central processing unit. By changing the fuse setting the characteristics of the central processing unit, and thus the microcontroller as a whole, can be changed.

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behaviour of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

Abstract: An improved clocking system for micro controllers is provided. The micro controller has two mechanisms by which the clocking is provided. One clock is provided by an external clock signal which is generally crystal controlled. A second mechanism for providing the clock is also present. This second clock can be useful as the "primary" or first clock which is generally a crystal oscillator may take several milliseconds to stabilize following a restart from a stop mode. The second clock mechanism can for example be an internal ring oscillator or other type of clock which although not as accurate as a crystal clock does not require the several milliseconds to recover.