Patents by Inventor Joseph Tsang

Joseph Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7908329
    Abstract: Various technologies and techniques are disclosed that enhance the security of electronic mail messages and folders. Messages that are deemed to be less secure and have a higher security risk, such as unsolicited commercial e-mail (i.e. SPAM) and phishing messages, are reformatted and displayed in plain text with hyperlinks disabled in certain circumstances. For example, messages in a junk e-mail folder may be reformatted and displayed in plain text with hyperlinks disabled to make them safer for the user to interact with.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: March 15, 2011
    Assignee: Microsoft Corporation
    Inventors: Brian Joseph Tsang, Stanley Grant, Lubdha Khandelwai, Robert Pengelly, Joseph Xavier
  • Publication number: 20070095250
    Abstract: An ink relating to an ink composition comprising: an ink vehicle; a colorant; and an additive effective to improve media independence of hue and chroma produced with said colorant.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 3, 2007
    Inventors: Linda Uhlir-Tsang, Hiang Lauw, Joseph Tsang
  • Publication number: 20070098927
    Abstract: The present invention relates to ink compositions including ink additives for controlling the color of the ink composition to provide media independence, improve black dye neutrality, and improve individual dye selection for a dye set, methods for producing the ink compositions, and methods using the ink compositions having the ink additives are disclosed.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventors: Linda Uhlir-Tsang, Mary Austin, Hiang Lauw, Joseph Tsang
  • Publication number: 20060201383
    Abstract: In accordance with embodiments of the present invention, an ink-jet ink can comprise a metallized phthalocyanine dye and a liquid vehicle carrying the dye. The liquid vehicle can include an amine additive present in the ink-jet ink at an effective concentration to cause improvement of ozone fastness. The improvement can be determined by comparing the ozone fastness of the ink-jet ink with a control ink-jet ink that does not include the amine additive.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 14, 2006
    Inventors: John Moffatt, Linda Uhlir-Tsang, Joseph Tsang
  • Publication number: 20050095470
    Abstract: Representative embodiments provide for a fuel activation device including a fuel storage chamber configured to store a plurality of fuel pellets arranged as a stack. A fuel dispensing device is configured to transport a fuel pellet to a fuel activation chamber. A spring is configured to advance the fuel pellets toward the fuel dispensing device as one or more fuel pellets are removed from the stack. A fuel initiator is configured to activate a release of hydrogen gas from the transported fuel pellet. The fuel activation device is configured to provide the hydrogen gas to a fuel cell through a gas vent. A method is provided including providing a plurality of fuel pellets arranged as a spring-loaded stack, transporting a fuel pellet from the stack, activating a release of hydrogen gas from the transported fuel pellet, and providing the hydrogen gas to a fuel cell.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 5, 2005
    Inventors: Philip Harding, Louis Barinaga, John Greeven, Paul McClelland, Joseph Tsang, Makarand Gore
  • Publication number: 20050074511
    Abstract: The present invention is drawn toward systems and methods for free-form fabrication of solid three-dimensional objects. In one embodiment, a solid free-form fabrication system for producing a three-dimensional object can comprise a dispensing system adapted to dispense a build material having nanofiller particulates dispersed therein; and a curing system adapted to harden the build material after being dispensed. In another embodiment, a method for producing a three-dimensional object can comprise steps of a) forming a jettable build composition including build material having nanofiller particulates dispersed therein; b) jetting a portion of the build composition to form a build layer; c) curing the build layer; and d) repeating steps b) and c), wherein multiple build layers are contacted and accrued to form a three-dimensional object.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 7, 2005
    Inventors: Christopher Oriakhi, Isaac Farr, Laura Kramer, Joseph Tsang
  • Patent number: 6073243
    Abstract: A flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks each having a memory cell. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. The control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit. The control circuitry may also be configured to receive a passcode that causes the control circuitry to override one of the block lock-bits.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 6, 2000
    Assignee: Intel Corporation
    Inventors: Vishram Prakash Dalvi, Rodney R. Rozman, Christopher John Haid, Jerry Kreifels, Joseph Tsang, Jeff Evertt, Jahanshir J. Javanifard, Jeffrey J. Peterson
  • Patent number: 6035401
    Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: March 7, 2000
    Assignee: Intel Corporation
    Inventors: Vishram Prakash Dalvi, Rodney R. Rozman, Christopher John Haid, Jerry Kreifels, Joseph Tsang, Jeff Evertt, Jahanshir J. Javanifard, Jeffrey J. Peterson
  • Patent number: 5954818
    Abstract: A method of writing to flash memory cells in a flash memory device. The flash memory device includes a first memory array and a second independent memory array. The first memory array includes memory blocks each having a memory cell. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes the steps of issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: September 21, 1999
    Assignee: Intel Corporation
    Inventors: Vishram Prakash Dalvi, Rodney R. Rozman, Christopher John Haid, Jerry Kreifels, Joseph Tsang, Jeff Evertt, Jahanshir J. Javanifard, Jeffrey J. Peterson
  • Patent number: RE42551
    Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: July 12, 2011
    Inventors: Vishram Prakash Dalvi, Rodney R. Rozman, Christopher John Haid, Jerry Kreifels, Joseph Tsang, Jeff Evertt, Jahanshir J. Javanifard, Jeffrey J. Peterson