Patents by Inventor Joseph V. Pierson

Joseph V. Pierson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stabilization of MOS-FET type voltage to current converters
    Patent number: 5394025
    Abstract: An electric power dissipation system operates as an active load for power supply testing. The system has a closed loop voltage to current converter with a first and second load terminal. A capacitance is connected across the first and second load terminals. A power supply having a first and second output terminal is coupled to the first and second load terminals via test conductors which have a first and second inductance respectively. A correction signal generator is provided to be responsive to the power supply. The correction signal generator provides an output signal as a function of the voltage generated across one of the inductances. A summing circuit responds to the output signal of the correction signal generator and also responds to a command signal. The output of the summing circuit controls the current flow of the current converter.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: February 28, 1995
    Assignee: Lambda Electronics, Inc.
    Inventor: Joseph V. Pierson