Abstract: Methods, apparatus, processors, and computer program products for obtaining or providing search results are provided. A method of providing search results includes receiving a query initiated by a user and performing a search based on the query. The method further includes determining a friends bias associated with the user, biasing a search result based on the friends bias, and storing the biased search results. Further provided is a method for obtaining search results that includes receiving a query initiated by a user and forwarding the query for performance of a search. Further included in the method is receiving and storing a biased search result in response to the query. The biased search result is based on friends bias data.

Abstract: Semiconductor devices, circuits and methods apply both system logic tests and external interface tests via a common series of boundary shift registers residing on the semiconductor chip. In an exemplary embodiment, a test access port receives an external testing signal from a source outside the semiconductor device, and an on-chip test module (e.g. a built-in self-test (BIST) module) contained within the semiconductor device provides an internal testing signal for the system logic. Control logic selectively provides appropriate input testing signals to the boundary shift registers and receives and processes appropriate output signals from the boundary shift registers in each testing mode. Using the various control techniques, a common set of boundary scan registers may be used to implement, for example, an IEEE 1149.1 interface, a BIST isolation wrapper scan chain, a BIST-mode input/output control, or the like.

Abstract: Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG) values. The pseudo-random vectors generated by the set of PRPG values are simulated, and those vectors best suited for an IDDQ test are selected. Each of the IDDQ vectors are identified in a test pattern. During subsequent testing, an IDDQ test of the semiconductor chip can be performed whenever the current test vector applied by the logic BIST corresponds to one of the predetermined IDDQ states.