Patents by Inventor Joseph Varghese
Joseph Varghese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11688632Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: GrantFiled: December 29, 2020Date of Patent: June 27, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20230177218Abstract: A computer-implemented method of ensuring integrity of an integrated circuit (IC) is provided. The computer-implemented method includes providing a design layer that meets design rule checks (DRCs), identifying a first critical dimension (CD) distribution of the design layer and using retargeting shapes in the design layer to enable a biasing of CDs of targets to enable a provision of two different CD distributions, which are DRC clean and which are separate from one another and which cannot be expressed by a single Gaussian distribution.Type: ApplicationFiled: December 8, 2021Publication date: June 8, 2023Inventors: Scott David Halle, Shawn Peter Fetterolf, Gauri Karve, Kangguo Cheng, Alex Joseph Varghese, Derren Neylon Dunn
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Publication number: 20230171114Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Dallas Lea, Yann Mignot, Marc A. Bergendahl, Alex Joseph Varghese, Sean Teehan, Andrew M. Greene, Matthew T. Shoudy
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Patent number: 11222956Abstract: In some embodiments, a semiconductor structure can include: a diamond substrate having a surface conductive layer; a heavily doped region formed in the diamond substrate; and a metal contact positioned over the conductive surface layer such that a first portion of the heavily doped region is covered by the metal contact and a second portion of the heavily doped region is not covered by the metal contact.Type: GrantFiled: April 9, 2020Date of Patent: January 11, 2022Assignee: Massachusetts Institute of TechnologyInventors: Joseph Varghese, Timothy Grotjohn, Michael Geis
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Patent number: 11152483Abstract: According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.Type: GrantFiled: September 17, 2019Date of Patent: October 19, 2021Assignee: Massachusetts Institute of TechnologyInventors: Michael Geis, Joseph Varghese, Robert Nemanich
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Publication number: 20210320183Abstract: In some embodiments, a semiconductor structure can include: a diamond substrate having a surface conductive layer; a heavily doped region formed in the diamond substrate; and a metal contact positioned over the conductive surface layer such that a first portion of the heavily doped region is covered by the metal contact and a second portion of the heavily doped region is not covered by the metal contact.Type: ApplicationFiled: April 9, 2020Publication date: October 14, 2021Inventors: Joseph Varghese, Timothy Grotjohn, Michael Geis
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Patent number: 11114382Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.Type: GrantFiled: October 19, 2018Date of Patent: September 7, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex Joseph Varghese, Richard A. Conti, Su Chen Fan
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Publication number: 20210151351Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: ApplicationFiled: December 29, 2020Publication date: May 20, 2021Inventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20210083070Abstract: According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Michael Geis, Joseph Varghese, Robert Nemanich
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Patent number: 10923401Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.Type: GrantFiled: October 26, 2018Date of Patent: February 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew Greene, Marc Bergendahl, Ekmini A. De Silva, Alex Joseph Varghese, Yann Mignot, Matthew T. Shoudy, Gangadhara Raja Muthinti, Dallas Lea
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Patent number: 10903111Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: GrantFiled: March 20, 2019Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20200303246Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Inventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20200135575Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Andrew Greene, Marc Bergendahl, Ekmini A. De Silva, Alex Joseph Varghese, Yann MIGNOT, Matthew T. Shoudy, GANGADHARA RAJA MUTHINTI, DALLAS LEA
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Publication number: 20200126926Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: Alex Joseph Varghese, Richard A. Conti, Su Chen Fan
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Publication number: 20140081706Abstract: A brand monitoring platform (BMP) for brand benchmarking based on a brand's social media strength is provided. The BMP acquires input information on the brand and identifies industries related to the brand and competing brands. The BMP acquires social media information related to the brand and the competing brands from multiple social media sources via a network, dynamically generates categories in one or more hierarchical levels in each of the industries based on an independent analysis of the social media information, and sorts the social media information into the categories using a sorting interface. The BMP generates an aggregate score using an audience score determined by measuring an aggregate reach of the brand and the competing brands based on weighted audience score metric parameters, and an engagement score determined by measuring interaction between the brand and the competing brands and their followers based on weighted engagement score metric parameters.Type: ApplicationFiled: November 21, 2013Publication date: March 20, 2014Applicant: Unmetric, Inc.Inventors: Joseph Varghese, Kumaravel Krishnasami, Lakshmanan Narayan
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Patent number: 8620718Abstract: A brand monitoring platform (BMP) for brand benchmarking based on a brand's social media strength is provided. The BMP acquires input information on the brand and identifies industries related to the brand and competing brands. The BMP acquires social media information related to the brand and the competing brands from multiple social media sources via a network, dynamically generates categories in one or more hierarchical levels in each of the industries based on an independent analysis of the social media information, and sorts the social media information into the categories using a sorting interface. The BMP generates an aggregate score using an audience score determined by measuring an aggregate reach of the brand and the competing brands based on weighted audience score metric parameters, and an engagement score determined by measuring interaction between the brand and the competing brands and their followers based on weighted engagement score metric parameters.Type: GrantFiled: August 17, 2012Date of Patent: December 31, 2013Assignee: Unmetric Inc.Inventors: Joseph Varghese, Kumaravel Krishnasami, Lakshmanan Narayan
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Publication number: 20130325550Abstract: A brand monitoring platform (BMP) for brand benchmarking based on a brand's social media strength is provided. The BMP acquires input information on the brand and identifies industries related to the brand and competing brands. The BMP acquires social media information related to the brand and the competing brands from multiple social media sources via a network, dynamically generates categories in one or more hierarchical levels in each of the industries based on an independent analysis of the social media information, and sorts the social media information into the categories using a sorting interface. The BMP generates an aggregate score using an audience score determined by measuring an aggregate reach of the brand and the competing brands based on weighted audience score metric parameters, and an engagement score determined by measuring interaction between the brand and the competing brands and their followers based on weighted engagement score metric parameters.Type: ApplicationFiled: August 17, 2012Publication date: December 5, 2013Inventors: Joseph Varghese, Kumaravel Krishnasami, Lakshmanan Narayan
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Publication number: 20070032640Abstract: A crystalline composition comprising a crystal of the IL-6 receptor I chain is provided. Also provided are methods of using the crystal and related structural information to screen for and design compounds that interact with IL-6R, or variants thereof. Also provided arc methods of modulating an IL-6 receptor comprising contacting the IL-6 receptor with a compound identified by the screening method of the invention.Type: ApplicationFiled: September 16, 2002Publication date: February 8, 2007Inventors: Joseph Varghese, Richard Simpson, Robert Moritz, Meizhen Lou, Hong Ji, Kim Branson, Brian Smith
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Patent number: 5452239Abstract: An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.Type: GrantFiled: February 26, 1993Date of Patent: September 19, 1995Assignee: Quickturn Design Systems, Inc.Inventors: Wei-Jin Dai, Louis Galbiati, III, Joseph Varghese, Dam V. Bui, Stephen P. Sample