Patents by Inventor Joseph Varghese

Joseph Varghese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930735
    Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Min Gyu Sung, Sony Varghese, Anthony Renau, Morgan Evans, Joseph C. Olson
  • Patent number: 10923401
    Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Greene, Marc Bergendahl, Ekmini A. De Silva, Alex Joseph Varghese, Yann Mignot, Matthew T. Shoudy, Gangadhara Raja Muthinti, Dallas Lea
  • Patent number: 10903111
    Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
  • Patent number: 10873543
    Abstract: An FC fabric login/logout system includes an FC switch device coupled to an endpoint device by an intermediate FC fabric device. The intermediate FC fabric device receives a first FC fabric login from the endpoint device and, in response, performs FC fabric login operations to create an FC fabric session between the endpoint device and the FC switch device, and stores FC fabric session information in hardware table(s). When the intermediate FC fabric device determines that an FC fabric session time period has passed, it ends the FC fabric session by clearing the FC fabric session information from the hardware table(s), and stores the FC fabric session information in software table(s). If the intermediate FC fabric device then receives a second FC fabric login from the endpoint device, it recreates the FC fabric session by transferring the FC fabric session information from the software table(s) to the hardware table(s).
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 22, 2020
    Assignee: Dell Products L.P.
    Inventors: Vibin Varghese, Ramesh Kumar Subbiah, Joseph LaSalle White
  • Publication number: 20200303246
    Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 24, 2020
    Inventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
  • Publication number: 20200244599
    Abstract: An FC fabric login/logout system includes an FC switch device coupled to an endpoint device by an intermediate FC fabric device. The intermediate FC fabric device receives a first FC fabric login from the endpoint device and, in response, performs FC fabric login operations to create an FC fabric session between the endpoint device and the FC switch device, and stores FC fabric session information in hardware table(s). When the intermediate FC fabric device determines that an FC fabric session time period has passed, it ends the FC fabric session by clearing the FC fabric session information from the hardware table(s), and stores the FC fabric session information in software table(s). If the intermediate FC fabric device then receives a second FC fabric login from the endpoint device, it recreates the FC fabric session by transferring the FC fabric session information from the software table(s) to the hardware table(s).
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Inventors: Vibin Varghese, Ramesh Kumar Subbiah, Joseph LaSalle White
  • Publication number: 20200185228
    Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Applicant: APPLIED Materials, Inc.
    Inventors: Min Gyu Sung, Sony Varghese, Anthony Renau, Morgan Evans, Joseph C. Olson
  • Publication number: 20200135575
    Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Andrew Greene, Marc Bergendahl, Ekmini A. De Silva, Alex Joseph Varghese, Yann MIGNOT, Matthew T. Shoudy, GANGADHARA RAJA MUTHINTI, DALLAS LEA
  • Publication number: 20200126926
    Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Inventors: Alex Joseph Varghese, Richard A. Conti, Su Chen Fan
  • Publication number: 20200123866
    Abstract: A wireline cable includes an electrically conductive cable core for transmitting electrical power. The wireline cable further includes an inner layer of a plurality of first armor wires surrounding the cable core and an outer layer of a plurality of second armor wires surrounding the inner layer, wherein a diameter of the outer layer of the plurality of second armor wires is smaller than a diameter of the inner layer of the plurality of first armor wires.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 23, 2020
    Inventors: Joseph Varkey, Mathew Varghese, Sheng Chang, Tam Tran
  • Patent number: 10607847
    Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 31, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Min Gyu Sung, Sony Varghese, Anthony Renau, Morgan Evans, Joseph C. Olson
  • Publication number: 20140081706
    Abstract: A brand monitoring platform (BMP) for brand benchmarking based on a brand's social media strength is provided. The BMP acquires input information on the brand and identifies industries related to the brand and competing brands. The BMP acquires social media information related to the brand and the competing brands from multiple social media sources via a network, dynamically generates categories in one or more hierarchical levels in each of the industries based on an independent analysis of the social media information, and sorts the social media information into the categories using a sorting interface. The BMP generates an aggregate score using an audience score determined by measuring an aggregate reach of the brand and the competing brands based on weighted audience score metric parameters, and an engagement score determined by measuring interaction between the brand and the competing brands and their followers based on weighted engagement score metric parameters.
    Type: Application
    Filed: November 21, 2013
    Publication date: March 20, 2014
    Applicant: Unmetric, Inc.
    Inventors: Joseph Varghese, Kumaravel Krishnasami, Lakshmanan Narayan
  • Patent number: 8620718
    Abstract: A brand monitoring platform (BMP) for brand benchmarking based on a brand's social media strength is provided. The BMP acquires input information on the brand and identifies industries related to the brand and competing brands. The BMP acquires social media information related to the brand and the competing brands from multiple social media sources via a network, dynamically generates categories in one or more hierarchical levels in each of the industries based on an independent analysis of the social media information, and sorts the social media information into the categories using a sorting interface. The BMP generates an aggregate score using an audience score determined by measuring an aggregate reach of the brand and the competing brands based on weighted audience score metric parameters, and an engagement score determined by measuring interaction between the brand and the competing brands and their followers based on weighted engagement score metric parameters.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: December 31, 2013
    Assignee: Unmetric Inc.
    Inventors: Joseph Varghese, Kumaravel Krishnasami, Lakshmanan Narayan
  • Publication number: 20130325550
    Abstract: A brand monitoring platform (BMP) for brand benchmarking based on a brand's social media strength is provided. The BMP acquires input information on the brand and identifies industries related to the brand and competing brands. The BMP acquires social media information related to the brand and the competing brands from multiple social media sources via a network, dynamically generates categories in one or more hierarchical levels in each of the industries based on an independent analysis of the social media information, and sorts the social media information into the categories using a sorting interface. The BMP generates an aggregate score using an audience score determined by measuring an aggregate reach of the brand and the competing brands based on weighted audience score metric parameters, and an engagement score determined by measuring interaction between the brand and the competing brands and their followers based on weighted engagement score metric parameters.
    Type: Application
    Filed: August 17, 2012
    Publication date: December 5, 2013
    Inventors: Joseph Varghese, Kumaravel Krishnasami, Lakshmanan Narayan
  • Publication number: 20070032640
    Abstract: A crystalline composition comprising a crystal of the IL-6 receptor I chain is provided. Also provided are methods of using the crystal and related structural information to screen for and design compounds that interact with IL-6R, or variants thereof. Also provided arc methods of modulating an IL-6 receptor comprising contacting the IL-6 receptor with a compound identified by the screening method of the invention.
    Type: Application
    Filed: September 16, 2002
    Publication date: February 8, 2007
    Inventors: Joseph Varghese, Richard Simpson, Robert Moritz, Meizhen Lou, Hong Ji, Kim Branson, Brian Smith
  • Patent number: 5452239
    Abstract: An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: September 19, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Wei-Jin Dai, Louis Galbiati, III, Joseph Varghese, Dam V. Bui, Stephen P. Sample