Patents by Inventor Joseph W. Cowan

Joseph W. Cowan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6864563
    Abstract: A configuration including a grounding mechanism protects a semiconductor device from electrical overstress damage during processes, such as an RIE process, where an electrical charge can build up on the semiconductor device. According to an exemplary embodiment, the configuration secures a semiconductor device such that a die of the device is exposed to an electrically charged environment and electrically conductive terminals of the device are isolated from the electrically charged environment. The grounding mechanism electrically connects each of the electrically conductive terminals to a ground potential while the die is exposed to the electrically charged environment.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: March 8, 2005
    Assignee: LSI Logic Corporation
    Inventor: Joseph W. Cowan
  • Patent number: 6817004
    Abstract: A method of displaying a net in a CAD layout for an integrated circuit chip includes steps for receiving a netlist of an integrated circuit design, displaying a CAD layout of the netlist, selecting a net segment in the CAD layout, and displaying a physical characteristics list of information items representative of physical characteristics of the net segment.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: November 9, 2004
    Assignee: LSI Logic Corporation
    Inventors: Joseph W. Cowan, Jeffrey E. Blackwood, Tracy D. Myers
  • Publication number: 20040143809
    Abstract: A method of displaying a net in a CAD layout for an integrated circuit chip includes steps for receiving a netlist of an integrated circuit design, displaying a CAD layout of the netlist, selecting a net segment in the CAD layout, and displaying a physical characteristics list of information items representative of physical characteristics of the net segment.
    Type: Application
    Filed: January 22, 2003
    Publication date: July 22, 2004
    Inventors: Joseph W. Cowan, Jeffrey E. Blackwood, Tracy D. Myers
  • Patent number: 6747473
    Abstract: The present invention concerns an apparatus comprising a first plurality of contacts, a second plurality of contacts, one or more sockets, and a programmable processor. The first plurality of contacts may be configured to receive one or more first signals. The second plurality of contacts may be configured to present one or more second signals in response to the one or more first signals. The one or more sockets may be configured to receive one or more third signals from one or more programmable devices. The programmable processor may be configured to generate a test signal in response to (i) the one or more first signals and (ii) the one or more third signals.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 8, 2004
    Assignee: LSI Logic Corporation
    Inventor: Joseph W. Cowan
  • Publication number: 20040059971
    Abstract: The present invention concerns an apparatus comprising a first plurality of contacts, a second plurality of contacts, one or more sockets, and a programmable processor. The first plurality of contacts may be configured to receive one or more first signals. The second plurality of contacts may be configured to present one or more second signals in response to the one or more first signals. The one or more sockets may be configured to receive one or more third signals from one or more programmable devices. The programmable processor may be configured to generate a test signal in response to (i) the one or more first signals and (ii) the one or more third signals.
    Type: Application
    Filed: September 23, 2002
    Publication date: March 25, 2004
    Applicant: LSI LOGIC CORPORATION
    Inventor: Joseph W. Cowan
  • Patent number: 6605951
    Abstract: Interconnectors are placed on a die containing a semiconductor device or integrated circuit which is to be tested or analyzed. The interconnector includes a bump contact for contacting a bond pad of the die, and a probe pad at a position spaced from the bump contact. An interconnector connects the bump contact and the probe pad. The interconnector is attached to the die with the bump contact in electrical contact with the bond pad and with the probe pad extending beyond an exterior peripheral edge of the die. Probes apply signals or power to the probe pad, and those signals and power are applied to the semiconductor device or integrated circuit to establish functionality for the test or analysis.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: August 12, 2003
    Assignee: LSI Logic Corporation
    Inventor: Joseph W. Cowan
  • Patent number: 6140581
    Abstract: An electrically grounded semiconductor structure is embedded in a non-conductive packaging material, without employing any electrical leads of the semiconductor structure as an electrical path and without damaging the semiconductor structure. The desired grounding connection is obtained by physically removing a portion of the non-conductive packaging material from a rear portion of the semiconductor structure, replacing the removed non-conductive material by a conformable electrically conductive material, and then electrically contacting this conformable electrically conductive material to a grounding element. In another aspect of the invention, a portion of the non-conductive packaging material is removed from a rear portion of the semiconductor structure and a metallic element such as a pin or a spring is disposed to make contact between the exposed portion of the semiconductor structure and the grounding element.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: October 31, 2000
    Assignee: Mitsubishi Electronics America, Inc.
    Inventors: Joseph W. Cowan, Tom Taylor, J. Neil Schunke