Patents by Inventor Joseph W. Triece
Joseph W. Triece has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9921985Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.Type: GrantFiled: September 21, 2015Date of Patent: March 20, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Joseph W. Triece, Rodney J. Pesavento, Gregg D. Lahti, Steven Dawson
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Publication number: 20160011998Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Applicant: Microchip Technology IncorporatedInventors: Joseph W. Triece, Rodney J. Pesavento, Gregg D. Lahti, Steven Dawson
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Patent number: 9208095Abstract: A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.Type: GrantFiled: October 30, 2007Date of Patent: December 8, 2015Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Rodney J. Pesavento, Gregg D. Lahti, Joseph W. Triece
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Patent number: 9141572Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.Type: GrantFiled: October 30, 2007Date of Patent: September 22, 2015Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Joseph W. Triece, Rodney J. Pesavento, Gregg D. Lahti, Steven Dawson
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Patent number: 8825912Abstract: A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.Type: GrantFiled: September 22, 2009Date of Patent: September 2, 2014Assignee: Microchip Technology IncorporatedInventors: Gregg Lahti, Rodney Pesavento, Joseph W. Triece, D. C. Sessions
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Patent number: 8779734Abstract: An integrated circuit device has a digital device operating at an internal core voltage; a linear voltage regulator; and an internal switched mode voltage regulator controlled by the digital device and receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins.Type: GrantFiled: December 7, 2011Date of Patent: July 15, 2014Assignee: Microchip Technology IncorporatedInventors: Bryan Kris, Joseph W. Triece, J. Clark Rogers, Pieter Schieke
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Patent number: 8650356Abstract: A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.Type: GrantFiled: May 7, 2010Date of Patent: February 11, 2014Assignee: Microchip Technology IncorporatedInventors: Tim L. Wilson, Joseph W. Triece, Steven G. Dawson
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Patent number: 8650341Abstract: A controller area network (CAN) controller unit has a message assembly buffer receiving a serial bitstream, a buffer memory coupled in parallel with said message assembly buffer, a CAN control unit coupled with the message assembly and the buffer memory, and at least one control register. The at least one control register can be programmed to cause the CAN control unit to store a message received in the message assembly register in at least a first and second mode, wherein in the first mode, control information and data payload of the received CAN message are stored in the buffer memory and in the second mode only the data payload of the CAN message is stored in the buffer memory.Type: GrantFiled: April 12, 2010Date of Patent: February 11, 2014Assignee: Microchip Technology IncorporatedInventors: Steven G. Dawson, Tim L. Wilson, Joseph W. Triece
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Publication number: 20130147446Abstract: An integrated circuit device has a digital device operating at an internal core voltage; a linear voltage regulator; and an internal switched mode voltage regulator controlled by the digital device and receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Inventors: Bryan Kris, Joseph W. Triece, J. Clark Rogers, Pieter Schieke
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Patent number: 8117475Abstract: A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power mode and in an active mode, and a direct memory access (DMA) controller operating independently from the CPU and operable to operate in a sleep or low power mode and in an active mode, wherein the DMA controller is further operable to transfer data from and to a memory or peripheral device, wherein when the system is in a sleep or low power mode, only the DMA controller and any system component which is necessary to perform a DMA transaction are switched into active mode.Type: GrantFiled: October 30, 2007Date of Patent: February 14, 2012Assignee: Microchip Technology IncorporatedInventors: Rodney J. Pesavento, Joseph W. Triece
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Patent number: 7966457Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.Type: GrantFiled: October 30, 2007Date of Patent: June 21, 2011Assignee: Microchip Technology IncorporatedInventors: Rodney J. Pesavento, Gregg D. Lahti, Joseph W. Triece
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Patent number: 7877537Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.Type: GrantFiled: October 30, 2007Date of Patent: January 25, 2011Assignee: Microchip Technology IncorporatedInventors: Rodney J. Pesavento, Gregg D. Lahti, Joseph W. Triece
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Publication number: 20110007759Abstract: A controller area network (CAN) controller unit has a message assembly buffer receiving a serial bitstream, a buffer memory coupled in parallel with said message assembly buffer, a CAN control unit coupled with the message assembly and the buffer memory, and at least one control register. The at least one control register can be programmed to cause the CAN control unit to store a message received in the message assembly register in at least a first and second mode, wherein in the first mode, control information and data payload of the received CAN message are stored in the buffer memory and in the second mode only the data payload of the CAN message is stored in the buffer memory.Type: ApplicationFiled: April 12, 2010Publication date: January 13, 2011Inventors: Steven G. Dawson, Tim L. Wilson, Joseph W. Triece
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Publication number: 20100306457Abstract: A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.Type: ApplicationFiled: May 7, 2010Publication date: December 2, 2010Inventors: Tim L. Wilson, Joseph W. Triece, Steven G. Dawson
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Patent number: 7788434Abstract: An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.Type: GrantFiled: October 30, 2007Date of Patent: August 31, 2010Assignee: Microchip Technology IncorporatedInventors: Rodney J. Pesavento, Joseph W. Triece
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Publication number: 20100121988Abstract: A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.Type: ApplicationFiled: September 22, 2009Publication date: May 13, 2010Inventors: Gregg Lahti, Rodney Pesavento, Joseph W. Triece, D.C. Sessions
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Patent number: 7603601Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.Type: GrantFiled: February 16, 2006Date of Patent: October 13, 2009Assignee: Microchip Technology IncorporatedInventors: Cristian P. Masgras, Michael Pyska, Edward Brian Boles, Joseph W. Triece, Igor Wojewoda, Mei-Ling Chen
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Patent number: 7401176Abstract: Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted in order to achieve an index of a literal offset address mode.Type: GrantFiled: October 20, 2004Date of Patent: July 15, 2008Assignee: Microchip Technology IncorporatedInventors: Joshua M. Conner, James H. Grosbach, Joseph W. Triece
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Publication number: 20080147946Abstract: An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.Type: ApplicationFiled: October 30, 2007Publication date: June 19, 2008Inventors: Rodney J. Pesavento, Joseph W. Triece
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Publication number: 20080147979Abstract: A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.Type: ApplicationFiled: October 30, 2007Publication date: June 19, 2008Inventors: Rodney J. Pesavento, Gregg D. Lahti, Joseph W. Triece