Patents by Inventor Joseph W. Wiseman

Joseph W. Wiseman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573552
    Abstract: A semiconductor device includes a gate electrode disposed on a fin, a gate spacer disposed on the fin and a sidewall of the gate electrode, a source/drain electrode disposed on the fin, and an air pocket structure interposed between the gate spacer and the source/drain electrode. The air pocket structure includes an air gap, a first sidewall, a top sealing, a second sidewall and a bottom sealing. The air gap is enclosed by the first sidewall, the top sealing, the second sidewall and the bottom sealing arranged in a clockwise sequence. The top sealing and the bottom sealing include the same material of an energy removable material.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joseph W Wiseman, Suraj K Patil
  • Publication number: 20190287849
    Abstract: A semiconductor device includes a gate electrode disposed on a fin, a gate spacer disposed on the fin and a sidewall of the gate electrode, a source/drain electrode disposed on the fin, and an air pocket structure interposed between the gate spacer and the source/drain electrode. The air pocket structure includes an air gap, a first sidewall, a top sealing, a second sidewall and a bottom sealing. The air gap is enclosed by the first sidewall, the top sealing, the second sidewall and the bottom sealing arranged in a clockwise sequence. The top sealing and the bottom sealing include the same material of an energy removable material.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 19, 2019
    Inventors: Joseph W. WISEMAN, Suraj K. PATIL
  • Patent number: 8643083
    Abstract: Devices and systems for insulating integrated circuits from ultraviolet (“UV”) light are described. The device includes a conductive feature, a first and second UV blocking layer, a first and second insulating laver, and a conductive structure. The first insulating layer overlays the first UV blocking layer. A via opening extends through the first insulating layer and the first UV blocking layer. The second UV blocking layer overlays the first insulating laver. The second insulating layer overlays the second UV blocking layer. An interconnect trench is defined in the second insulating layer and second UV blocking layer. The conductive structure is electrically connected to the conductive feature and extends into the via opening and along the interconnect trench.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Spansion LLC
    Inventors: Bryon K. Hance, Brian D. White, William Brennan, Joseph W. Wiseman, Allen Evans
  • Publication number: 20120218700
    Abstract: An electronic device can include a conductive feature and an ultraviolet (“UV”) blocking layer overlying the conductive feature. The electronic device can also include an insulating layer overlying the UV blocking layer. The electronic device can further include a conductive structure extending into an opening within the insulating layer, wherein the conductive structure is electrically connected to the conductive feature. In one aspect, the UV blocking layer lies within 90 nm of the conductive structure. The insulating layer can be at least 4 times thicker than the UV blocking layer. In another aspect, a method can be used in forming the electronic device. In still a further aspect, a system can include the electronic device, a processor, and a display, wherein the processor is electrically coupled to the electronic device and the display.
    Type: Application
    Filed: May 7, 2012
    Publication date: August 30, 2012
    Applicant: SPANSION LLC
    Inventors: Bryon K. Hance, Brian D. White, William Brennan, Joseph W. Wiseman, Allen Evans
  • Patent number: 8171627
    Abstract: A process of forming an electronic device including forming a first ultraviolet (“UV”) blocking layer over a conductive feature, wherein the first UV blocking layer lies within 90 nm of the conductive structure; forming a first insulating layer over the first UV blocking layer; and patterning the first insulating layer and the first UV blocking layer to form a first opening extending to the conductive feature, wherein during the process, the first UV blocking layer is exposed to UV radiation.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: May 8, 2012
    Assignee: Spansion LLC
    Inventors: Bryon K. Hance, Brian D. White, William Brennan, Joseph W. Wiseman, Allen Evans
  • Publication number: 20090159321
    Abstract: An electronic device can include a conductive feature and an ultraviolet (“UV”) blocking layer overlying the conductive feature. The electronic device can also include an insulating layer overlying the UV blocking layer. The electronic device can further include a conductive structure extending into an opening within the insulating layer, wherein the conductive structure is electrically connected to the conductive feature. In one aspect, the UV blocking layer lies within 90 nm of the conductive structure. The insulating layer can be at least 4 times thicker than the UV blocking layer. In another aspect, a method can be used in forming the electronic device. In still a further aspect, a system can include the electronic device, a processor, and a display, wherein the processor is electrically coupled to the electronic device and the display.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicant: Spansion LLC
    Inventors: Bryon K. Hance, Brian D. White, William Brennan, Joseph W. Wiseman, Allen Evans