Abstract: A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.

Abstract: A clock splitter circuit for providing a single event upset (SEU) tolerant clock signal to latches in a space-based environment. The clock splitter circuit can include one or more event offset circuit delay circuits. The event offset delay receives a clock signal and generates a delayed clock signal. The event offset delay circuit can generate an inverted clock signal, a delayed inverted clock signal and a pair of intermediate clock signals. The delayed clock signal and inverted delayed clock signal can be delayed by the known duration of single event effects (SEE). The delayed and undelayed clock signals can be passed to an event blocking filter which can block any disturbance in the delayed and/or undelayed clock signals. A synchronizer can synchronize outputs of the event blocking filter prior to or coincident with being passed to corresponding inverting clock drivers. The synchronizers can also insure that the synchronized blocking filter outputs can not be low simultaneously.

Abstract: The improved register file includes an array of storage cells arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch applies its decoded output to a multiplexer which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array. The output storage cell array is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array stores the data from the selected read lines out of the multiplexer.

Abstract: A CMOS flip-flop circuit is disclosed which enables a single side pull-down operation for inputting test signals during a test mode and alternately a dual side push-pull operation for inputting data signals during the normal use of the circuit. A pair of inverter circuits selectively feed complementary data signals to opposite sides of a bistable circuit so that the circuit operates in the push-pull manner thereby decreasing the switching time of the flip-flop. A pair of transmission gates, which are coupled to outputs of the inverter circuits, electrically isolate any noise appearing at a data input from the bistable circuit. During a test mode of the flip-flop, a test signal is fed into one side of the bistable circuit and facilitates a single side pull-down operation of the flip-flop. Two such flip-flop circuits are concatenated in a push-pull cascaded connection to provide a shift register latch.

Abstract: A soft error protection circuit is disclosed for a storage cell, such as a latch having a first input/output node and a second input/output node which are respectively connected to a charging source, the first node being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor having a diffusion electrode connected to the second node and having a gate electrode, for selectively loading the second node with an additional capacitance. An inverter circuit has an input connected to the second node and an output connected to the gate electrode of the capacitor, for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node.