Abstract: A system and method for thermally testing integrated circuits, comprising a temperature generation device located within the IC, configured with a primary purpose of affecting a temperature at the IC. A temperature sensor is located within close proximity to the IC, and a temperature controller is coupled to the temperature generation device and to the temperature sensor.

Abstract: A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-test (BIST) circuit on the chip, in accordance with the initial algorithm; collecting a set of failure information in response to testing; and transmitting the failure information from the chip to the computer over the communications link. The present invention's system includes: a communications link; a computer, operating a set of chip testing software; and a chip under test coupled to the computer by the communications link, having, a memory array; and a BIST module for testing the memory array in response to test algorithms received from the computer and transmitting those addresses within the memory array which failed testing.

Abstract: A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second time interval within the first time interval. A delay timer, coupled between the first and second timers, pseudo-randomly delays initiation of the second timer from the start of the first time interval. In one embodiment, the first timer is an (N+1)-bit binary counter. The delay timer includes an N-bit round robin latch and seeded by a pseudo-random number generator having fewer than N bits, the round robin latch shifting its contents to form an N-bit pseudo-random number. The second timer is initiated when the value of the first timer is equivalent to the round robin latch. A coincidence circuit passes digital event pulses during the second time interval. A count is accumulated of the sampled digital event pulses.

Abstract: An apparatus and method for monitoring memory system performance and controlling an operating parameter is provided. A plurality of digital events indicative of memory system operations is detected, from which a subset of digital events to count is periodically selected, the subset being those digital events occurring during a sampling window time interval. Responsive to each digital event of the subset, a transistor is switched on to conduct current from a power supply to a capacitor. The transistor is biased by the capacitor to operate in a constant current region providing a substantially fixed amount of charge added to the capacitor responsive to each digital event of the subset. The operating parameter is controlled responsive to the charge accumulated in the capacitor, representative of the count of digital events in the subset. In one embodiment, the sampling window time interval is selected pseudo-randomly within a periodic base time interval.

Abstract: An analog performance monitoring method and circuit arrangement are adapted to count a plurality of digital event pulses. Each digital event pulse controls a switching circuit to pass a substantially fixed amount of charge from a power supply. The charge is accumulated in a capacitor. In one example embodiment, the switching circuit is a transistor biased by the capacitor voltage to operate in a constant current region. The capacitor has a capacity to accumulate charge added from at least 100,000 digital event pulses maintaining bias of transistor operation in the constant current region. A comparator circuit monitors capacitor charge and signals when a quantity of events adding charge to the capacitor reaches a selectable threshold. In another example embodiment, a programmable voltage divider provides a controllable threshold. A reset circuit discharges the capacitor to an approximate ground level. Sampling is used to estimate a population of digital event pulses.

Abstract: A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second time interval within the first time interval. A delay timer, coupled between the first and second timers, pseudo-randomly delays initiation of the second timer from the start of the first time interval. In one embodiment, the first timer is an (N+1)-bit binary counter. The delay timer includes an N-bit round robin latch and seeded by a pseudo-random number generator having fewer than N bits, the round robin latch shifting its contents to form an N-bit pseudo-random number. The second timer is initiated when the value of the first timer is equivalent to the round robin latch. A coincidence circuit passes digital event pulses during the second time interval. A count is accumulated of the sampled digital event pulses.

Abstract: An apparatus and method for monitoring memory system performance and controlling an operating parameter is provided. A plurality of digital events indicative of memory system operations is detected, from which a subset of digital events to count is periodically selected, the subset being those digital events occurring during a sampling window time interval. Responsive to each digital event of the subset, a transistor is switched on to conduct current from a power supply to a capacitor. The transistor is biased by the capacitor to operate in a constant current region providing a substantially fixed amount of charge added to the capacitor responsive to each digital event of the subset. The operating parameter is controlled responsive to the charge accumulated in the capacitor, representative of the count of digital events in the subset. In one embodiment, the sampling window time interval is selected pseudo-randomly within a periodic base time interval.

Abstract: An analog performance monitoring method and circuit arrangement are adapted to approximately count a plurality of digital event pulses. Each digital event pulse controls a switching circuit to pass a substantially fixed amount of charge from a power supply. The charge is accumulated in a capacitor. In one example embodiment, the switching circuit is a transistor biased by the capacitor voltage to operate in a constant current region. The capacitor has a capacity to accumulate charge added from at least 100,000 digital event pulses maintaining bias of transistor operation in the constant current region. A comparator circuit monitors capacitor charge and signals when a quantity of events adding charge to the capacitor reaches a selectable threshold. In another example embodiment, a programmable voltage divider provides a controllable threshold. A reset circuit discharges the capacitor to an approximate ground level. Sampling is used to estimate a population of digital event pulses.

Abstract: A high-density low-cost read-only memory circuit is disclosed. Within the memory circuit, a passive device chip, including only passive devices is configured to form a read-only memory array; and an active device chip, having supporting circuitry electrically coupled to the memory array. The passive chip may include amorphous or poly-Silicon diodes; the supporting circuitry may include bit-line, word-line, address decoder; sense amplifier, and output driver circuitry. The memory array may further include a first memory array; and a second memory array, deposited upon the first memory array layer, together forming a three-dimensional multi-layer compact memory circuit. The passive and active chips may be coupled together and encapsulated within a multi-chip module (MCM) package. The MCM package may further include any number of additional passive memory arrays connected to the active chip.

Abstract: A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-test (BIST) circuit on the chip, in accordance with the initial algorithm; collecting a set of failure information in response to testing; and transmitting the failure information from the chip to the computer over the communications link. The present invention's system includes: a communications link; a computer, operating a set of chip testing software; and a chip under test coupled to the computer by the communications link, having, a memory array; and a BIST module for testing the memory array in response to test algorithms received from the computer and transmitting those addresses within the memory array which failed testing.

Abstract: Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Abstract: A high-density low-cost read-only memory circuit is disclosed. Within the memory circuit, a passive device chip, including only passive devices is configured to form a read-only memory array; and an active device chip, having supporting circuitry electrically coupled to the memory array. The passive chip may include amorphous or poly-Silicon diodes; the supporting circuitry may include bit-line, word-line, address decoder; sense amplifier, and output driver circuitry. The memory array may further include a first memory array; and a second memory array, deposited upon the first memory array layer, together forming a three-dimensional multi-layer compact memory circuit. The passive and active chips may be coupled together and encapsulated within a multi-chip module (MCM) package. The MCM package may further include any number of additional passive memory arrays connected to the active chip.