Patents by Inventor Joseph William Buckfeller
Joseph William Buckfeller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7137400Abstract: Described herein are apparatuses, methods and systems to monitor the performance of one or more mass flow controllers that supply gases to deposition, etching, and other manufacturing processes. A bypass loop is provided in fluid connection from either the process line or the vent line. In the bypass loop is a flow detector, such as a digitized mass flow controller. The flow detector takes one or more measurements of flow of gas from a mass flow controller, and data from such one or more measurements is used to provide information about the accuracy and/or precision of the mass flow controller. Also disclosed are ways to correct for back pressure or back vacuum in the process line.Type: GrantFiled: September 30, 2003Date of Patent: November 21, 2006Assignee: Agere Systems Inc.Inventors: William Daniel Bevers, Robert Francis Jones, Bennett J. Ross, Joseph William Buckfeller, James L. Flack
-
Publication number: 20040250600Abstract: A method and apparatus for monitoring or calibrating a gas flow rate through a mass flow controller, for example, in a semiconductor fabrication process. A reference mass flow controller is disposed in a vent bypass loop for receiving gas flow from one of a plurality of mass flow controllers associated with a like plurality of supply gases. One of the gas supply mass flow controllers is selected and commanded to a specific gas flow rate. The gas flow through the selected mass flow controller also passes through the reference mass flow controller as the gas flows to a vent. Comparing the gas supply mass flow controller commanded flow rate with the actual flow rate as determined by the reference mass flow controller provides monitoring and calibration of the gas supply mass flow controller.Type: ApplicationFiled: May 12, 2004Publication date: December 16, 2004Inventors: William Daniel Bevers, Joseph William Buckfeller, James L. Flack, Robert Francis Jones, Bennett J. Ross
-
Publication number: 20040106279Abstract: A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.Type: ApplicationFiled: November 12, 2003Publication date: June 3, 2004Inventors: Steven Mark Anderson, Siddhartha Bhowmik, Joseph William Buckfeller, Sailesh Mansinh Merchant, Frank Minardi
-
Patent number: 6720261Abstract: A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.Type: GrantFiled: June 2, 2000Date of Patent: April 13, 2004Assignee: Agere Systems Inc.Inventors: Steven Mark Anderson, Siddhartha Bhowmik, Joseph William Buckfeller, Sailesh Mansinh Merchant, Frank Minardi
-
Patent number: 6169036Abstract: A method is for cleaning via openings during manufacturing of integrated circuits. The method preferably comprises the steps of sputter cleaning the via opening at least once, and exposing the via opening to a reducing atmosphere at least once. The method may include alternatingly repeating the sputter cleaning and exposing steps. The step of sputter cleaning is preferably performed prior to the step of exposing, and a sputter cleaning may be performed after a last step of exposing the via opening to the reducing atmosphere. In one embodiment, the exposed metal portion comprises a metal compound, such as an oxide. Accordingly, the step of sputter cleaning removes at least a portion of the metal oxide, and the step of exposing comprises reducing at least a portion of the metal oxide. The invention is particularly applicable when the metal interconnection layer is a copper, as copper readily oxides at its exposed surface.Type: GrantFiled: March 25, 1999Date of Patent: January 2, 2001Assignee: Lucent Technologies Inc.Inventors: Siddhartha Bhowmik, Joseph William Buckfeller, G. Craig Clabough, Sailesh Mansinh Merchant
-
Patent number: 6136159Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an antireflective coating to prevent rainbowing or spiking of the coating into the underlying metal.Type: GrantFiled: November 6, 1998Date of Patent: October 24, 2000Assignee: Lucent Technologies Inc.Inventors: Joseph William Buckfeller, Sailesh Chittipeddi, Sailesh Mansinh Merchant
-
Patent number: 5935396Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.Type: GrantFiled: April 25, 1997Date of Patent: August 10, 1999Assignee: Lucent Technologies Inc.Inventors: Joseph William Buckfeller, Sailesh Chittipeddi, Sailesh Mansinh Merchant
-
Patent number: 5807760Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.Type: GrantFiled: September 3, 1996Date of Patent: September 15, 1998Assignee: Lucent Technologies Inc.Inventors: Joseph William Buckfeller, Sailesh Chittipeddi, Sailesh Mansinh Merchant