Abstract: In some examples, an electronic device includes a host processor, a security processor separate from the host processor, and a management controller separate from the host processor. The security processor loads agent instructions associated with the security processor to the management controller, and sends, from the security processor to the agent instructions executing on the management controller, an indication to execute identified machine-readable instructions. The agent instructions when executed on the management controller cause the management controller to, based on the indication, execute the identified machine-readable instructions that employ a resource of the management controller, and provide, from the management controller to the security processor, a result of a process that employs the resource of the management controller.

Abstract: A technique includes measuring, by a self-validation engine of an integrated circuit, the integrated circuit to provide a hardware integrity measurement. The technique includes  generating, by the self-validation engine, an observed fingerprint for the integrated circuit based on the hardware integrity measurement and a firmware integrity measurement. The technique includes validating, by the self-validation engine, the integrated circuit based on the observed fingerprint.

Abstract: In some examples, an electronic device includes a host processor, a security processor separate from the host processor, and a management controller separate from the host processor. The security processor loads agent instructions associated with the security processor to the management controller, and sends, from the security processor to the agent instructions executing on the management controller, an indication to execute identified machine-readable instructions. The agent instructions when executed on the management controller cause the management controller to, based on the indication, execute the identified machine-readable instructions that employ a resource of the management controller, and provide, from the management controller to the security processor, a result of a process that employs the resource of the management controller.

Abstract: In some examples, a security apparatus includes a security processor to control access to an encryption key in a memory region protected by the security apparatus. The security apparatus further includes a memory region controller that receives a request for the encryption key from an encryption engine associated with a management controller, the request being based on a memory alias provided from the management controller to the encryption engine, where the management controller is to invoke the encryption engine to encrypt data using the encryption key. Based on the request, the memory region controller provides the encryption key to the encryption engine.

Abstract: A process includes providing a first signal to a first conductive mesh of a semiconductor package to provide a wireless transmission, and receiving, by a second conductive mesh of the semiconductor package, the wireless transmission to provide a second signal. The process includes determining a signature of the second signal and generating, by a cryptographic security parameter generator of the semiconductor package, a cryptographic security parameter based on the signature.

Abstract: In some examples, a controller receives, from a validator system in an electronic device, input information including address information identifying a memory region in a memory to validate. The memory is associated with a target system to be validated and the memory is inaccessible to the validator system. Based on the address information, the controller retrieves information from the memory region in the memory, where the controller provides a barrier that prevents access of the retrieved information by the validator system. The controller computes a cryptographic value based on the retrieved information, and the controller sends, to the validator system, an output based on the cryptographic value as a response to the input information.

Abstract: In some examples, a system includes a nonvolatile memory to store information, and a controller subsystem to perform various tasks. The controller subsystem receives, from an entity, an input to trigger an erase verification operation after an erase of a memory region of the nonvolatile memory containing the information. The controller subsystem generates a pseudorandom pattern in response to the input, and writes the pseudorandom pattern to the memory region as part of the erase verification operation. After the writing, the controller subsystem provides, from the nonvolatile memory to the entity, the pseudorandom pattern retrieved from the memory region for verification that the erasing of the information of the memory region has occurred.

Abstract: A process includes providing a first signal to a first conductive mesh of a semiconductor package to provide a wireless transmission, and receiving, by a second conductive mesh of the semiconductor package, the wireless transmission to provide a second signal. The process includes determining a signature of the second signal and generating, by a cryptographic security parameter generator of the semiconductor package, a cryptographic security parameter based on the signature.

Abstract: Examples disclosed herein relate to processing health information of a computing device according to a deep learning model to determine whether an anomaly has occurred. Multiple computing devices can be part of a system. One of the computing devices includes a host processing element, a management controller separate from the host processing element, and a deep learning model that includes parameters that are trained to identify anomalistic behavior for the computing device. The management controller can receive health information from multiple components of the computing device and process the health information according to the deep learning model to determine whether an anomaly occurred.

Abstract: In some examples, a management controller includes a communication interface to communicate with a computing device, where the management controller is separate from a processor of the computing device. The management controller includes a management processor to receive, from the computing device, a first hash value that is based on a first hash function applied on an input value and a salt, generate a second hash value based on applying a second hash function on the first hash value and a pepper, and send the second hash value to the computing device.

Abstract: In some examples, a management controller includes a communication interface to communicate with a computing device, where the management controller is separate from a processor of the computing device. The management controller includes a management processor to perform a validation of program codes of virtual entities of the computing device, and in response to the validation of the program codes, unlock access of information in an information store to allow access of the information by the computing device, wherein the information is for use by the virtual entities of the computing device, and wherein the management processor is to block access of the information in the information store prior to the validation.

Abstract: In some examples, a management controller includes a communication interface to communicate with a computing device, where the management controller is separate from a processor of the computing device. The management controller includes a management processor to receive, from the computing device, a first hash value that is based on a first hash function applied on an input value and a salt, generate a second hash value based on applying a second hash function on the first hash value and a pepper, and send the second hash value to the computing device.

Abstract: In some examples, a management controller includes a communication interface to communicate with a computing device, where the management controller is separate from a processor of the computing device. The management controller includes a management processor to perform a validation of program codes of virtual entities of the computing device, and in response to the validation of the program codes, unlock access of information in an information store to allow access of the information by the computing device, wherein the information is for use by the virtual entities of the computing device, and wherein the management processor is to block access of the information in the information store prior to the validation.

Abstract: Examples disclosed herein relate to processing health information of a computing device according to a deep learning model to determine whether an anomaly has occurred. Multiple computing devices can be part of a system. One of the computing devices includes a host processing element, a management controller separate from the host processing element, and a deep learning model that includes parameters that are trained to identify anomalistic behavior for the computing device. The management controller can receive health information from multiple components of the computing device and process the health information according to the deep learning model to determine whether an anomaly occurred.

Abstract: Examples disclosed herein relate to using a baseboard management controller (BMC) to convey data between two networks. The BMC has a network interface. Before the BMC connects to a first network, it performs a security assessment including a check on a storage. Then the BMC receives and stores, on the storage, data from the first network. The network interface is then disconnected from the first network and connected to a second network. The data is conveyed to another device using the second network.

Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.

Abstract: A firmware controller of a node of a distributed system determines a self-regulation threshold for at least one metric associated with traffic transmitted via an interconnect. The threshold is set to a value lower than the maximum permitted by the interconnect protocol. The controller transmits a request to an application-layer traffic endpoint to limit traffic based on the threshold. A hardware congestion management unit collects measurements on traffic metrics, including at least one metric other than the one for which the threshold is defined. Based on measurements obtained from the hardware congestion management unit, the controller modifies the self-regulation threshold and notifies the application-layer endpoint.

Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.

Abstract: A firmware controller of a node of a distributed system determines a self-regulation threshold for at least one metric associated with traffic transmitted via an interconnect. The threshold is set to a value lower than the maximum permitted by the interconnect protocol. The controller transmits a request to an application-layer traffic endpoint to limit traffic based on the threshold. A hardware congestion management unit collects measurements on traffic metrics, including at least one metric other than the one for which the threshold is defined. Based on measurements obtained from the hardware congestion management unit, the controller modifies the self-regulation threshold and notifies the application-layer endpoint.

Abstract: An improved downhole battery control, monitoring, and management system is described wherein battery pack parameters can be measured and used to determine optimal and efficient battery usage scenarios for a downhole measurement system. A battery local controller network is configured and used to monitor, control, and manage the batteries deployed in a downhole measurement system. Battery parameters such as voltage, power usage, energy consumption, uptime, temperature, current, and other parameters may be monitored and/or communicated on the battery local controller network and used to make management decisions about which batteries to utilize in a given time period.