Abstract: An apparatus to time delay a digital, signal output from an oversampled sensor includes a first time delay element and a second time delay element. The first time delay element has a first input and a first output. The first time delay element is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. An output of the oversampled sensor is connected to the first input of the first time delay element. The second time delay element has a second input and a second output and is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. The first output of the first time delay element is connected to the second input of the second time delay element. A multiplexer has a control input and a multiplexer output. The first output of the first time delay element is connected to a first multiplexer input. The second output of the second time delay element is connected to a second multiplexer input.

Abstract: Programming time delay data in an oversampled sensor includes determining whether to enter Programming Mode based on a value of a system parameter received by the oversampled sensor. Programming Mode is entered when the value of the system parameter corresponds to Programming Mode. The time delay data is programmed in the oversampled sensor during Programming Mode. The oversampled sensor uses the time delay data to time delay its output in an oversampled domain. Programming Mode is exited after a predetermined time has expired relative to when Programming Mode was entered. The system parameter can be a frequency of a sampling clock signal.

Abstract: Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.

Abstract: Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.

Abstract: Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.

Abstract: Programming time delay data in an oversampled sensor includes determining whether to enter Programming Mode based on a value of a system parameter received by the oversampled sensor. Programming Mode is entered when the value of the system parameter corresponds to Programming Mode. The time delay data is programmed in the oversampled sensor during Programming Mode. The oversampled sensor uses the time delay data to time delay its output in an oversampled domain. Programming Mode is exited after a predetermined time has expired relative to when Programming Mode was entered. The system parameter can be a frequency of a sampling clock signal.

Abstract: An apparatus to time delay a digital, signal output from an oversampled sensor includes a first time delay element and a second time delay element. The first time delay element has a first input and a first output. The first time delay element is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. An output of the oversampled sensor is connected to the first input of the first time delay element. The second time delay element has a second input and a second output and is configured to output a time delayed signal that is time delayed by an integer number of sampling clock cycles. The first output of the first time delay element is connected to the second input of the second time delay element. A multiplexer has a control input and a multiplexer output. The first output of the first time delay element is connected to a first multiplexer input. The second output of the second time delay element is connected to a second multiplexer input.

Abstract: Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.

Abstract: Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC) The ADC includes a digital sensor responsive to an analog field quantity The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The fitter low pass filters and decimates tea lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.