Abstract: Embodiments herein describe a system that includes a first Faraday cage defining a first aperture through which a first conveyor extends, a first wirelessly controlled machine disposed in the first Faraday cage, where the first wirelessly controlled machine is configured to transmit control signals using a first frequency range, a second Faraday cage defining a second aperture through which a second conveyor extends, and a second wirelessly controlled machine disposed in the second Faraday cage where the first wirelessly controlled machine is configured to transmit control signals using the first frequency range. Further, a portion of at least one of the first Faraday cage and the second Faraday cage is disposed between the first and second apertures.

Abstract: Embodiments herein describe a controller for a machine that wirelessly transmits a destination address to a robot which is tasked with transporting an item to the destination corresponding to the received address. Using the address, the robot can select a predefined path stored in its memory for that address. Because multiple robots can move items in the machine at the same time, the robots may collide if their predefined paths intersect. The machine can use a variety of different techniques to prevent collisions between the robots as the robots deliver items to different locations along their predefined paths.

Abstract: Embodiments herein describe a system that includes a first Faraday cage defining a first aperture through which a first conveyor extends, a first wirelessly controlled machine disposed in the first Faraday cage, where the first wirelessly controlled machine is configured to transmit control signals using a first frequency range, a second Faraday cage defining a second aperture through which a second conveyor extends, and a second wirelessly controlled machine disposed in the second Faraday cage where the first wirelessly controlled machine is configured to transmit control signals using the first frequency range. Further, a portion of at least one of the first Faraday cage and the second Faraday cage is disposed between the first and second apertures.

Abstract: RF shielding techniques are employed to prevent wireless signals transmitted from one machine from reaching another machine using the same frequency range. If the machines are spaced closely together, the wireless signals emitted by one machine may be received by the other, thereby causing interference. In one embodiment, one of the machines is placed in a Faraday cage which prevents it from transmitting wireless signals to, and receiving signals from, the other machine. In another embodiment, machines that use different channels are grouped into a first Faraday cage while machines that use the same channels as the machines in the first Faraday cage are placed in a second Faraday cage. In this manner, the machines in the two cages can reuse the same communication channels while being disposed proximate to each other in the shared space.

Abstract: Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

Abstract: Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

Abstract: Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.