Abstract: A sensor for contactlessly detecting currents, has a sensor element having a magnetic tunnel junction (MTJ), and detection circuitry, the sensor element having a resistance which varies with the magnetic field, and the detection circuitry is arranged to detect a tunnel current flowing through the tunnel junction. The sensor element may share an MTJ stack with memory elements. Also it can provide easy integration with next generation CMOS processes, including MRAM technology, be more compact, and use less power. Solutions for increasing sensitivity of the sensor, such as providing a flux concentrator, and for generating higher magnetic fields with a same current, such as forming L-shaped conductor elements, are given. The greater sensitivity enables less post processing to be used, to save power for applications such as mobile devices. Applications include current sensors, built-in current sensors, and IDDQ and IDDT testing, even for next generation CMOS processes.

Abstract: The invention relates to a decoding method for decoding Low-Density Parity Check codes in transmission and recording systems. The method comprises a running minimum loop comprising the following iterative sub-steps:—reading a reliability value from the input sequence of input reliability values,—comparing said reliability value with a stored value,—overwriting the stored value with said reliability value if said reliability value is smaller than said stored value.

Abstract: The present invention provides a method and device for reconfiguring an embedded computing system during its lifetime, so that optimal trade-offs between performance and energy consumption can be achieved. An embedded computing system (10) according to the present invention comprises a plurality of domains, each domain (80, 82) comprising at least one processing element (12), each domain (80, 82) operating at a utility supply value, one domain (80, 82) having a first utility supply value. Each processing element (12) of the one domain is provided with a reconfiguration device for independently changing the utility supply value to a second utility supply value for the one domain.

Abstract: Sliding-window decoders with processor-systems (1) for decoding streams of symbols run prolog deriving processes (23) for deriving initial parameters for prolog-windows, and run main deriving processes (24) for deriving main parameters for main-windows thereby using initial conditions defined by said initial parameters. By introducing defining processes (22) for defining the prolog-windows having a flexible number of symbols, a flexible size, dependently upon the needed quality of the initial condition, the prolog-window can be made larger/smaller (initial condition with higher/lower quality). As a result, the efficiency is improved, as a consequence of the average overlap between prolog-windows of a certain main-window and a neighboring main-window being reduced. Preferably, per main-window, the prolog-windows get increasing sizes. Based upon the insight of initial conditions needing to have flexible qualities, the basic idea introduces flexible sizes for prolog-windows.

Abstract: The invention relates to a method for creating a waveform composed by superposition of N waves using a Coordinate Rotation Digital Computer (CORDIC). To provide for generation of composite waveforms said CORDIC calculates within N calculating steps discrete values of said N waves, and said output of said discrete values from said CORDIC is cumulated with previous outputs of discrete values to form a composed discrete value of said waveform.

Abstract: In a method of the invention for providing clock signals to a mixed signal telecommunication chip having a communication signal in a communication signal band, said clock signals comprise a central clock frequency signal and sub-frequency signals which are multiples or divisions of said central clock frequency signal. The central clock frequency signal is selected such that the central clock frequency signal and the sub-frequency signals are located outside the telecommunication signal band. The a mixed signal telecommunication chip of the invention takes advantage of the above clock planning.

Abstract: A DAB receiver in which a reduced time de-interleaving memory for storing metrics is used, but which still allows processing of DAB services which normally would exceed the storage capacity of the memory. This is achieved by varying the length of a stored metric, depending upon the storage capacity required, by varying the number of stored reliability bits in a metric. In this way, a trade-off can be made between storage capacity and processing quality.

Abstract: In a digital audio broadcast receiver a digital audio transmission signal is supplied to a demodulator which provides demodulation samples. The demodulation samples are de-interleaved in a first section of a de-interleaving memory. After having been de-interleaved, demodulation samples are transferred to a second section of the de-interleaving memory. This transfer is effectuated in bursts via a relatively small buffer which stores the bursts. The second section of the de-interleaving memory effectively constitutes a relatively large buffer. De-interleaved demodulations samples are regularly read from the second section and supplied as a regular stream to a Viterbi decoder by means of a relatively small first-in first-out register.

Abstract: When the processing circuitry of a signal processor can handle data at a faster rate than the rate of arrival of signal units to be processed, the processor is able to execute a cycle of microcodes for each arriving signal unit. To generate the cycle, the signal processor contains base address reproducing means, for in each cycle reproducing a standard sequence of successive base addresses BA(i) (i=1 . . . N). The base address reproducing means feed microcode selecting means for selecting, in step with each base address and under control of signal data received from the processing circuitry, an associated microcode address MA(i) from a repertory of microcode addresses indicated by the base address BA(i). Selection is implemented by adding each base address BA(i) to an associated index IA(i), determined in dependence on signal data received from the processing circuitry.

Abstract: A hardware-efficient data receiver in which the receiver digital baseband signal samples relate to the bits in the transmission signal. For each sample, a metric calculator calculates an input data element (metric) for the soft decision decoder in the receiver. The metric is a binary word of whose most significant bit (gross bit) indicates the most likely value (`0` or `1`) of a bit in the transmission signal. The other bits of the metric (reliability bits) express the reliability of this gross bit. The metric calculator has a monotonous transition function with equidistant steps between two extreme metric values (all metric bits are `0` or `1`). According to this transition function, the metric value varies as a function of the digital baseband signal sample value in a range bounded by two saturation values. The number of different sample values in this range, including the saturation values, is two to the power of an integer.

Abstract: A modified Booth multiplier for multiplying an m-bit number X by an n-bit number Y comprises a Booth encoder for converter the number Y in groups of 3 bits which overlap by 1 bit into a series Y' of multiplication values whose number is equal to or substantially equal to half the number of bits of Y. There is also provided a multiplex circuit for forming partial products from the number X and said series Y' and a matrix configuration of full adders for adding the partial products in incremental positions. The design is such that the constituent components and the operation of the modified Booth multiplier can be tested by means of a very small number of test patterns which are generated in the Booth multiplier after application of a specific series of X,Y-values.