Abstract: An arrangement for identifying and disassembling a series of instructions of variable length stored in a prefetch buffer includes a set of controlled multiplexer circuits for selectively transferring the contents of specified register of the prefetch buffer to a ring or loop-configured shift registers, termed a "byte rotator", which functions as a temporary adjustable storage device. That portion of the byte rotator which contains the opcode token of the instruction read out of the prefetch buffer is decoded to determine the length of each token. Once the length of the first token is known, it can be determined where the second or next token begins. In the same fashion, each successive token is transferred to the byte rotator until all tokens for the current instructions have been used. The next token is the opcode for the following instruction.

Abstract: A fast cache flush mechanism includes, associated with the cache, an auxiliary portion (termed a flush count memory) that references a flush counter during the addressing of the cache. This flush counter preferably has a count capacity of the same size as the number of memory locations in the cache. Whenever the cache is updated, the current value of the flush counter is written into the location in the flush count memory associated with the memory location in the cache pointed to by an accessing address, and the valid bit is set.Whenever it is desired to flush the cache, the contents of the flush counter are changed (e.g. incremented) to a new value which is then written as the new cache index into the location of the flush count memory associated with that flush count, and the associated valid bit is cleared or reset.