Patents by Inventor Josh Bowman

Josh Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230034585
    Abstract: Systems, devices, and methods for treating a nerve injury in a patient are provided. The system includes an extracellular matrix, a neutralizing element, and a reconstituting element. The extracellular matrix is configured to promote and/or sustain the growth of tissue and/or associated tissue properties proximate the nerve injury.
    Type: Application
    Filed: December 30, 2020
    Publication date: February 2, 2023
    Inventors: Lorenzo Soletti, Josh Bowman, Nicole Cwalina, Brandon Burger, J. Christopher Flaherty
  • Publication number: 20220323648
    Abstract: Systems, devices, and methods for treating a nerve injury in a patient are provided herein. The system includes an extracellular matrix, a neutralizing element, and a reconstituting element. The extracellular matrix is configured to promote and/or sustain the growth of tissue and/or associated tissue properties proximate the nerve injury.
    Type: Application
    Filed: September 30, 2020
    Publication date: October 13, 2022
    Inventors: Lorenzo Soletti, Bryan Brown, Josh Bowman, Nicole Cwalina, Brandon Burger, J. Christopher Flaherty
  • Patent number: 10649779
    Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen
  • Patent number: 10613868
    Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen
  • Patent number: 10498362
    Abstract: A system for an Error Correction Code (“ECC”) decoder includes a first decoder and a second decoder. The first decoder is configured to determine a first estimated number of errors in encoded data received at the first decoder and to compare the first estimated number of errors to a first threshold and a second threshold. The second decoder is configured to receive the encoded data when the first estimated number of errors is below the first threshold and is above a second threshold. When the first estimated number of errors is above the first threshold, the first decoder passes the encoded data out of the ECC. The first decoder has a lower power consumption than the second decoder.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Paul Hanham, Josh Bowman, David Symons
  • Publication number: 20180175882
    Abstract: A system for an Error Correction Code (“ECC”) decoder includes a first decoder and a second decoder. The first decoder is configured to determine a first estimated number of errors in encoded data received at the first decoder and to compare the first estimated number of errors to a first threshold and a second threshold. The second decoder is configured to receive the encoded data when the first estimated number of errors is below the first threshold and is above a second threshold. When the first estimated number of errors is above the first threshold, the first decoder passes the encoded data out of the ECC. The first decoder has a lower power consumption than the second decoder.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Inventors: Paul Hanham, Josh Bowman, David Symons
  • Publication number: 20180175885
    Abstract: A solid state storage device, comprising a non-volatile memory configured to store data encoded into a plurality of encoded data groups, each encoded data group of the plurality being encoded using a BCH or Hamming parity scheme, the plurality of encoded data groups being collectively further encoded by a parity scheme using a Low Density Parity Check (LDPC) code, a non-volatile memory controller communicatively coupled to the non-volatile memory and configured to access the plurality of encoded data groups, a first decoder configured to first decode the plurality of encoded data groups by hard-decision decoding the parity in each encoded data group, and a second decoder commutatively coupled to the first decoder and configured to determine the data groups decoded by the first decoder that contain errors, and to decode the parity of the data groups that contain errors using likelihood-of-errors information that is input to the second decoder.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Inventors: Paul Hanham, Josh Bowman, David Symons
  • Patent number: 9559565
    Abstract: Radial poles are placed around a radial actuator target mounted on a body. The poles are separated from a cylindrical surface of the target by radial gaps and adapted to communicate a magnetic flux with it. The radial poles are equipped with electrical control windings and magnetically coupled to form magnetic control circuits. A flux return pole is adjacent to the body, separated from it by an air gap and adapted to communicate a magnetic flux with the radial actuator target. A permanent magnet generates a magnetic bias flux in the magnetic bias circuit formed by the radial actuator target, the radial poles and the magnetic flux return pole. A radial force is exerted on the actuator when the control windings are energized with a current. A Hall effect sensor measures bias magnetic field in the air gap between the magnetic flux return pole and the body.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: January 31, 2017
    Assignee: Calnetix Technologies, LLC
    Inventors: Alexei Filatov, Josh Bowman
  • Publication number: 20170003969
    Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
    Type: Application
    Filed: June 30, 2015
    Publication date: January 5, 2017
    Inventors: Salma AYUB, Josh BOWMAN, Sundeep CHADHA, Dhivya JEGANATHAN, Cliff KUCHARSKI, Dung Q. NGUYEN
  • Publication number: 20170003971
    Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
    Type: Application
    Filed: March 17, 2016
    Publication date: January 5, 2017
    Inventors: Salma Ayub, Josh BOWMAN, Sundeep CHADHA, Dhivya JEGANATHAN, Cliff KUCHARSKI, Dung Q. NGUYEN
  • Publication number: 20160095473
    Abstract: A modular herb grinder. The grinder may include cooperating grinding modules that define a chamber for grinding herbs or the like. The grinder may also include one or more integrated tools related to smoking and/or preparing an apparatus for smoking.
    Type: Application
    Filed: April 16, 2015
    Publication date: April 7, 2016
    Inventors: Evan Perucca, Josh Bowman, Jeff Carabelos
  • Publication number: 20150054389
    Abstract: Radial poles are placed around a radial actuator target mounted on a body. The poles are separated from a cylindrical surface of the target by radial gaps and adapted to communicate a magnetic flux with it. The radial poles are equipped with electrical control windings and magnetically coupled to form magnetic control circuits. A flux return pole is adjacent to the body, separated from it by an air gap and adapted to communicate a magnetic flux with the radial actuator target. A permanent magnet generates a magnetic bias flux in the magnetic bias circuit formed by the radial actuator target, the radial poles and the magnetic flux return pole. A radial force is exerted on the actuator when the control windings are energized with a current. A Hall effect sensor measures bias magnetic field in the air gap between the magnetic flux return pole and the body.
    Type: Application
    Filed: July 28, 2014
    Publication date: February 26, 2015
    Inventors: Alexei Filatov, Josh Bowman