Patents by Inventor Josh Clyne

Josh Clyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Linear stage and metrology architecture for reflective electron beam lithography
    Patent number: 8724115
    Abstract: A stage metrology suitable for REBL includes an interferometer stage metrology system configured to measure the position and rotation of a short-stroke wafer scanning stage, wherein the interferometer metrology system includes two or more interferometers for each axis of measurement, wherein a first interferometer mirror is disposed on a first surface of the short-stroke wafer scanning stage and a second interferometer mirror is disposed on a second surface of the short-stroke wafer scanning stage, and a control system configured to determine a shape error for the first interferometer mirror using two or more interferometer measurements from the two or more interferometers associated with the first interferometer mirror and a shape error for the second interferometer mirror using two or more interferometer measurements from the two or more interferometers associated with the second interferometer mirror.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 13, 2014
    Assignee: KLA-Tencor Corporation
    Inventors: Upendra Ummethala, Layton Hale, Josh Clyne, Samir Nayfeh, Mark Williams, Joseph A. DiRegolo, Andrew Wilson
  • Linear Stage and Metrology Architecture for Reflective Electron Beam Lithography
    Publication number: 20130342827
    Abstract: A stage metrology suitable for REBL includes an interferometer stage metrology system configured to measure the position and rotation of a short-stroke wafer scanning stage, wherein the interferometer metrology system includes two or more interferometers for each axis of measurement, wherein a first interferometer mirror is disposed on a first surface of the short-stroke wafer scanning stage and a second interferometer mirror is disposed on a second surface of the short-stroke wafer scanning stage, and a control system configured to determine a shape error for the first interferometer mirror using two or more interferometer measurements from the two or more interferometers associated with the first interferometer mirror and a shape error for the second interferometer mirror using two or more interferometer measurements from the two or more interferometers associated with the second interferometer mirror.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 26, 2013
    Applicant: KLA-Tencor Corporation
    Inventors: Upendra Ummethala, Layton Hale, Josh Clyne, Samir Nayfeh, Mark Williams, Joseph A. DiRegolo, Andrew Wilson