Abstract: In a system of multiple caching agents accessing shared cache lines, a dynamic vector scaling mechanism is achieved through the selection of a mode to grant a caching agent that requests access to a cache line. Cache line entries in a directory indicate the particular caching agents that are sharing the line of cache. Modes may include a grouping of multiple caching agents or a representation of a single caching agent. A mode may be determined for additional caching agents. The selection and determination may include determining whether to maintain or change the modes of the caching agents. The selection of the modes for the caching agents may allow the vector to assume a representation in which the caching agents are grouped in such a way as to reduce a number of invalidation requests of a cache line.

Abstract: A directory for maintaining cache line entries may include a limited amount of space for the entries. A preemptive eviction of an entry of the directory is performed so that adequate space for a new entry may be created. The eviction may be performed when a system is in a low-activity state or an idle state in order to conserve system resources. Such a state may also ensure that the new entry does not have to wait to be entered into the directory. The eviction may include the examination of entries to determine if the contents may be eliminated from the directory. The system may establish certain criteria to aid in this determination. Once evicted from the directory, any modified data associated with the entry is transferred to a memory location.

Abstract: A system for tracking cache coherency in multiprocessor environment includes a first cell having a multiprocessor assembly, a memory, and a coherency director including a first intermediate home agent and a first intermediate cache agent. A second cell is similarly equipped. The two cells may share lines of cache in a controlled manner. Interconnection between the two cells connect the intermediate home agent of one cell to the intermediate cache agent of the second cell. Trackers are present in the agents of the first cell and the second cell. The trackers are responsible for keeping track of cache transactions between cells and queuing up requests for lines of cache so that retry attempts may be made. The trackers thus assist in transactions involving sharing lines of cache, exchanging information and resolving conflicts.

Abstract: A method and system for scaling upwards a multiprocessor cache coherency scheme includes at least two cells. Each cell containing a multiple processor assembly, a cache coherency director, and a system controller. The cache coherency director include an intermediate home agent (IHA) and an intermediate cache agent (ICA). An IHA in one cell communicates with an ICA in another cell to arbitrate the availability of lines of cache that are requested by a processor in one of the cells. A protocol that includes request retries avoids system lockups is used as the basis for inter-cell cache coherency communication.

Abstract: An apparatus containing a maintenance interface unit is described. In one exemplary implementation, the apparatus includes a multiprocessor system and the maintenance interface unit. The multiprocessor system uses cache coherency for accessing memory. The maintenance interface unit is integrated within the multiprocessor system and is configured to provide a backdoor accessibility to the multiprocessor system on-behalf of a peripheral maintenance system. The maintenance interface unit is also configured to perform operations within the multiprocessor system while maintaining the cache coherency.