Patents by Inventor Josh J. H. Feng

Josh J. H. Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Customized patterning modulation and optimization
    Patent number: 8806386
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chou Cheng, Ru-Gun Liu, Josh J. H. Feng, Tsong-Hua Ou, Luke Lo, Chih-Ming Lai, Wen-Chun Huang
  • Practical approach to layout migration
    Patent number: 8745554
    Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Josh J. H. Feng, Cheng-Lung Tsai, Ru-Gun Liu, Wen-Chun Huang
  • Dissection splitting with optical proximity correction and mask rule check enforcement
    Patent number: 8381153
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J. H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
  • DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION AND MASK RULE CHECK ENFORCEMENT
    Publication number: 20120072874
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J.H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
  • Practical Approach to Layout Migration
    Publication number: 20110161907
    Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Josh J.H. Feng, Cheng-Lung Tsai, Ru-Gun Liu, Wen-Chun Huang
  • CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION
    Publication number: 20110124193
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 26, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Chou Cheng, Ru-Gun Liu, Josh J.H. Feng, Tsong-Hua Ou, Luke Lo, Chih-Ming Lai, Wen-Chun Huang