Patents by Inventor Joshua A. Bell

Joshua A. Bell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Extracting wiring parasitics for filtered interconnections in an integrated circuit
    Patent number: 6766498
    Abstract: A method, system and computer program product for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (“interconnections of interest”). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mahesh S. Sharma, David M. Newmark, Teja Singh, Joshua A. Bell
  • Extracting wiring parasitics for filtered interconnections in an integrated circuit
    Publication number: 20040044974
    Abstract: A method, system and computer program product for extracting parasitic resistance and capacitance values to simulate performance of an integrated circuit. A selected number of interconnections in an integrated circuit may be identified (“interconnections of interest”). A netlist containing a list of the transistors in the integrated circuit may be pruned by selecting those transistors in the netlist that are in the channel connected regions on the driving side of the interconnections of interest and those on the receiving side of the interconnections of interest. Parasitic resistance and capacitance values for layout layers connected to the interconnections of interest may be extracted. These extracted parasitic resistance and capacitance values may be associated with the transistors connected to those layout layers in the pruned netlist.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 4, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mahesh S. Sharma, David M. Newmark, Teja Singh, Joshua A. Bell