Patents by Inventor Joshua Collins
Joshua Collins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240297075Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: May 13, 2024Publication date: September 5, 2024Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. VAN CLEEMPUT
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Publication number: 20240271281Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: April 3, 2024Publication date: August 15, 2024Inventors: Joshua COLLINS, Griffin John KENNEDY, Hanna BAMNOLKER, Patrick A. VAN CLEEMPUT, Seshasayee VARADARAJAN
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Publication number: 20240234152Abstract: Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: February 18, 2022Publication date: July 11, 2024Inventors: Lawrence Schloss, Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Sang-Hyeob Lee, Patrick van Cleemput, Sanjay Gopinath
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Patent number: 11970776Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: GrantFiled: January 27, 2020Date of Patent: April 30, 2024Assignee: Lam Research CorporationInventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Patrick A. van Cleemput, Seshasayee Varadarajan
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Publication number: 20240136192Abstract: Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: February 18, 2022Publication date: April 25, 2024Inventors: Lawrence Schloss, Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Sang-Hyeob Lee, Patrick van Cleemput, Sanjay Gopinath
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Publication number: 20240100658Abstract: A powered ratchet includes a motor, a mounting portion, and an output member configured to rotate in response to activation of the motor. The output member defines a drive axis. The powered ratchet also includes a release mechanism configured to selectively couple an anvil to the output member. The release mechanism includes a cover coupled to the mounting portion with a track and a locking member positioned between the mounting portion and the cover and operable to slide within the track between a locked position, in which the locking member engages the anvil to secure the anvil to the output member for co-rotation therewith, and a release position, in which the locking member is disengaged from the anvil to facilitate removal of the anvil. The release mechanism also includes a biasing member biasing the locking member to the locked position.Type: ApplicationFiled: February 18, 2022Publication date: March 28, 2024Inventors: Austin Clark, Carl N. Chandler, Matthew Samstag, Joshua Collins, James W. Jenkins, Ryan Altenburger, Gui Fang Zhou, Yu Zhao, Ping Zhang
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Publication number: 20230290680Abstract: Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to 10 the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.Type: ApplicationFiled: May 1, 2023Publication date: September 14, 2023Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Michal Danek, Shruti Vivek Thombare, Patrick A. van Cleemput, Gorun Butail
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Patent number: 11549175Abstract: Provided herein are methods and apparatuses for filling features metal-containing materials. One aspect of the disclosure relates to a method for filling structures with a metal-containing material, the method including: providing a structure to be filled with a metal-containing material, exposing the structure to multiple deposition cycles, with each deposition cycle including exposure to one or more alternating reducing agent (e.g. hydrogen (H2)) dose/inert gas purge pulses pulse followed by exposure to one or more alternating metal precursor dose pulses and inert gas purge pulses. The metal may be tungsten (W) or molybdenum (Mo) in some embodiments. In some embodiments, the structure is a partially fabricated (3-D) NAND structure. Apparatuses to perform the methods are also provided.Type: GrantFiled: May 3, 2019Date of Patent: January 10, 2023Assignee: Lam Research CorporationInventors: Gorun Butail, Joshua Collins, Hanna Bamnolker, Seshasayee Varadarajan
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Publication number: 20220375792Abstract: Embodiments of methods of filling features with molybdenum (Mo) include depositing a first layer of Mo in a feature including an opening and an interior and non-conformally treating the first layer such that regions near the opening preferentially treated over regions in the interior. In some embodiments, a second Mo layer is deposited on the treated first layer. Embodiments of methods of filling features with Mo include controlling Mo precursor flux to transition between conformal and non-conformal fill.Type: ApplicationFiled: October 14, 2020Publication date: November 24, 2022Inventors: Lawrence SCHLOSS, Shruti Vivek THOMBARE, Zhongbo YAN, Patrick A. VAN CLEEMPUT, Joshua COLLINS
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Publication number: 20220356579Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Joshua COLLINS, Griffin John KENNEDY, Hanna BAMNOLKER, Patrick A. VAN CLEEMPUT, Seshasayee VARADARAJAN
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Publication number: 20220262640Abstract: Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.Type: ApplicationFiled: May 5, 2022Publication date: August 18, 2022Inventors: Adam Jandl, Sema Ermez, Lawrence Schloss, Sanjay Gopinath, Michal Danek, Siew Neo, Joshua Collins, Hanna Bamnolker
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Publication number: 20220223471Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: January 31, 2022Publication date: July 14, 2022Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. van Cleemput
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Publication number: 20220213599Abstract: Vapor accumulator reservoirs for semiconductor processing operations, such as atomic layer deposition operations, are provided. Such vapor accumulator reservoirs may include a perimeter plenum volume filled with an inert gas, which may reduce or prevent the leakage of external contaminants into a process gas. In some implementations, the reservoir may be constructed from corrosion-resistant materials to reduce internal contaminants into the process gas.Type: ApplicationFiled: May 19, 2020Publication date: July 7, 2022Applicant: Lam Research CorporationInventors: Gary Bridger Lind, Panya Wongsenakhum, Joshua Collins, Harald te Nijenhuis
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Publication number: 20220195598Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: January 27, 2020Publication date: June 23, 2022Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Patrick A. van Cleemput, Seshasayee Varadarajan
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Patent number: 11355345Abstract: Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.Type: GrantFiled: December 21, 2019Date of Patent: June 7, 2022Assignee: Lam Research CorporationInventors: Adam Jandl, Sema Ermez, Lawrence Schloss, Sanjay Gopinath, Michal Danek, Siew Neo, Joshua Collins, Hanna Bamnolker
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Patent number: 11225712Abstract: A method for depositing tungsten includes arranging a substrate including a titanium nitride layer in a substrate processing chamber and performing multi-stage atomic layer deposition of tungsten on the substrate using a precursor gas includes tungsten chloride (WCIx) gas, wherein x is an integer. The performing includes depositing the tungsten during a first ALD stage using a first dose intensity of the precursor gas, and depositing the tungsten during a second ALD stage using a second dose intensity of the precursor gas. The first dose intensity is based on a first dose concentration and a first dose period. The second dose intensity is based on a second dose concentration and a second dose period. The second dose intensity is 1.5 to 10 times the first dose intensity.Type: GrantFiled: February 25, 2019Date of Patent: January 18, 2022Assignee: LAM RESEARCH CORPORATIONInventors: Joshua Collins, Siew Neo, Hanna Bamnolker, Kapil Umesh Sawlani
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Publication number: 20210238736Abstract: Provided herein are methods and apparatuses for filling features metal-containing materials. One aspect of the disclosure relates to a method for filling structures with a metal-containing material, the method including: providing a structure to be filled with a metal-containing material, exposing the structure to multiple deposition cycles, with each deposition cycle including exposure to one or more alternating reducing agent (e.g. hydrogen (H2)) dose/inert gas purge pulses pulse followed by exposure to one or more alternating metal precursor dose pulses and inert gas purge pulses. The metal may be tungsten (W) or molybdenum (Mo) in some embodiments. In some embodiments, the structure is a partially fabricated (3-D) NAND structure. Apparatuses to perform the methods are also provided.Type: ApplicationFiled: May 3, 2019Publication date: August 5, 2021Inventors: Gorun Butail, Joshua Collins, Hanna Bamnolker, Seshasayee Varadarajan
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Publication number: 20200402846Abstract: Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.Type: ApplicationFiled: November 19, 2018Publication date: December 24, 2020Applicant: Lam Research CorporationInventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Michal Danek, Shruti Vivek Thombare, Patrick van Cleemput, Gorun Butail
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Publication number: 20200365456Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: July 27, 2020Publication date: November 19, 2020Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick van Cleemput
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Patent number: 10777453Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: GrantFiled: November 6, 2019Date of Patent: September 15, 2020Assignee: Lam Research CorporationInventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput