Patents by Inventor Joshua D. Friedrich

Joshua D. Friedrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9952651
    Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Malcolm S. Allen-Ware, Michael S. Floyd, Joshua D. Friedrich, Charles R. Lefurgy, Kirk D. Peterson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Gregory S. Still, Brian W. Thompto, Victor Zyuban
  • Patent number: 9778726
    Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Malcolm S. Allen-Ware, Michael S. Floyd, Joshua D. Friedrich, Charles R. Lefurgy, Kirk D. Peterson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Gregory S. Still, Brian W. Thompto, Victor Zyuban
  • Publication number: 20170031415
    Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Malcolm S. ALLEN-WARE, Michael S. FLOYD, Joshua D. FRIEDRICH, Charles R. LEFURGY, Kirk D. PETERSON, Karthick RAJAMANI, Srinivasan RAMANI, Todd J. ROSEDAHL, Gregory S. STILL, Brian W. THOMPTO, Victor ZYUBAN
  • Publication number: 20170031417
    Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.
    Type: Application
    Filed: August 24, 2015
    Publication date: February 2, 2017
    Inventors: Malcolm S. ALLEN-WARE, Michael S. FLOYD, Joshua D. FRIEDRICH, Charles R. LEFURGY, Kirk D. PETERSON, Karthick RAJAMANI, Srinivasan RAMANI, Todd J. ROSEDAHL, Gregory S. STILL, Brian W. THOMPTO, Victor ZYUBAN
  • Patent number: 9541935
    Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John F. Bulzacchelli, Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still
  • Publication number: 20150123633
    Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
    Type: Application
    Filed: January 13, 2015
    Publication date: May 7, 2015
    Inventors: John F. Bulzacchelli, Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still
  • Patent number: 8981829
    Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still
  • Publication number: 20150061744
    Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
    Type: Application
    Filed: August 13, 2014
    Publication date: March 5, 2015
    Inventors: John F. Bulzacchelli, Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still
  • Patent number: 8812879
    Abstract: A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Huajun Wen, Joshua D. Friedrich, Norman K. James, Seongwon Kim, John R. Ripley, Edmund J. Sprogis
  • Publication number: 20140167832
    Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Alan Drake, Joshua D. Friedrich, Jason D. Hibbeler, Liang-Teck Pang, William R. Reohr, Phillip John Restle, Gregory S. Still, Michael G.R. Thomson
  • Patent number: 8736342
    Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan Drake, Joshua D. Friedrich, Jason D. Hibbeler, Liang-Teck Pang, William R. Reohr, Phillip John Restle, Gregory S. Still, Michael G. R. Thomson
  • Patent number: 8635478
    Abstract: During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Chase, Joshua D. Friedrich, Andrew J. Geissler, Soraya Ghiasi, Norman K. James, Jagat V. Pokala, Malcolm S. Ware
  • Publication number: 20120198255
    Abstract: During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.
    Type: Application
    Filed: December 29, 2011
    Publication date: August 2, 2012
    Applicant: International Business Machines Corporation
    Inventors: Harold W. Chase, Joshua D. Friedrich, Andrew J. Geissler, Soraya Ghiasi, Norman K. James, Jagat V. Pokala, Malcolm S. Ware
  • Patent number: 8122312
    Abstract: A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Joshua D. Friedrich, Robert B. Gass, Norman K. James
  • Publication number: 20110161682
    Abstract: A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: International Business Machines Corporation
    Inventors: Huajun Wen, Joshua D. Friedrich, Norman K. James, Seongwon Kim, John R. Ripley, Edmund J. Sprogis
  • Publication number: 20100262879
    Abstract: A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 14, 2010
    Applicant: International Business Machines Corporation
    Inventors: Michael S. Floyd, Joshua D. Friedrich, Robert B. Gass, Norman K. James
  • Publication number: 20100094572
    Abstract: Methods, apparatus, and computer program products are described for dynamic frequency and voltage scaling for a computer processor, including identifying during manufacture a nominal operating point of frequency and voltage for a computer processor, the nominal operating point including a nominal operating voltage identified for a design nominal operating frequency; determining, in dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function; and storing, in non-volatile storage on the computer processor during manufacture, information specifying the nominal operating point and the operating range.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold W. Chase, Joshua D. Friedrich, Soraya Ghiasi, Norman K. James, Jagat V. Pokala