Abstract: A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.

Abstract: A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.

Abstract: A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.