Abstract: An apparatus includes a bloom transistor frontend configured to receive an integrator output voltage and generate a comparator input voltage. The apparatus also includes a comparator configured to generate an output signal based on whether the comparator input voltage meets or exceeds a reference voltage. The bloom transistor frontend includes a first transistor configured to charge an input capacitance associated with the comparator in order to change the comparator input voltage. The bloom transistor frontend also includes a second transistor configured to discharge the input capacitance associated with the comparator in order to reset the comparator input voltage.

Abstract: An apparatus includes a bloom transistor frontend configured to receive an integrator output voltage and generate a comparator input voltage. The apparatus also includes a comparator configured to generate an output signal based on whether the comparator input voltage meets or exceeds a reference voltage. The bloom transistor frontend includes a first transistor configured to charge an input capacitance associated with the comparator in order to change the comparator input voltage. The bloom transistor frontend also includes a second transistor configured to discharge the input capacitance associated with the comparator in order to reset the comparator input voltage.

Abstract: An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.

Abstract: An image capturing device is provided, which includes a capacitive trans-impedance amplifier (CTIA) unit cell. The CTIA unit cell includes an image detector and a switching network. The image detector is configured to detect light having a first color and light having a second color different from the first color, and to generate a photocurrent in response to detecting the light. The switching network includes a CTIA switch, a CTIA low reset switch, and a CTIA high-reset biasing switch. The CTIA switch sets a first reset level of the CTIA unit cell to a first voltage in response invoking a first switching state of the CTIA low-reset switch and sets a second reset level of the CTIA to a second voltage greater than the first voltage level in response to invoking a second switching state of the CTIA low-reset switch.

Abstract: A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.

Abstract: An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.

Abstract: A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.

Abstract: An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.

Abstract: An integration capacitor network for connection to a photo-current source includes: an input; a first path connected between the input and a reset voltage, the first path including a first integration capacitor and a first cascode transistor, the first cascode transistor coupled between the input and the first integration capacitor; and a second path connected between the input and the reset voltage, the second path including a second integration capacitor and a second cascode transistor, the second cascode transistor coupled between the input and the second integration capacitor. Gates of the first and second cascode transistors are connected to a reference voltage and charge is accumulated on the first integration capacitor until a voltage on the first integration capacitor exceeds the reference voltage and then charge is accumulated on the second integration capacitor.