Abstract: Aspects of this disclosure relate to detecting a header of a packet. A receive signal path can provide a receive signal that includes packets and a guard preamble between successive packets of the packets. A receiver control circuit can trigger a timer that sets a time for detecting a header of a packet in response to detecting an end of a preamble of the packet.

Abstract: Aspects of this disclosure relate to detecting a header of a packet. A receive signal path can provide a receive signal that includes packets and a guard preamble between successive packets of the packets. A receiver control circuit can trigger a timer that sets a time for detecting a header of a packet in response to detecting an end of a preamble of the packet.

Abstract: A memory is organized into blocks. In a bit-flipping operation, a memory block is read, the read bit data values are inverted, and the inverted data is written back to the memory block. Inverted memory blocks are tracked by setting a flag bit in the memory block, or by storing a pointer to a memory block. In a read operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the read data values are reverted before being returned. In a write operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the write data values are inverted before being written. Inversion of data values and tracking of inverted memory blocks may be performed by a specialized memory controller or by a processor executing secure memory code. Data remanence is thus prevented in the memory.

Abstract: A memory is organized into blocks. In a write operation, data to be stored is combined with an address-dependent value (ADV) to form a block of information, and this block is encrypted. The block of encrypted information is written into a block of memory identified by the write address of the write operation. In a read operation, the block of encrypted information is read back from the memory and is decrypted to recover the data and the ADV. The address of the memory block from which the block of encrypted information was read is used to check the ADV to confirm that the ADV is related in the proper way to the address of the memory block that stored the encrypted information. If the check fails, the processor is prevented from executing the data, thereby preventing the processor from executing blocks of code that are in incorrect locations in memory.

Abstract: Upon execution of an interrupt return (IRET) instruction when a second interrupt is pending, rather than popping a stack, obtaining processor state information, and then pushing the state information back onto the stack prior to vectoring off to a second interrupt service routine, direct vectoring is employed such that the stack is not pushed or popped but rather the processor vectors directly from the IRET instruction in the first interrupt service routine to the second interrupt service routine. A novel stored interrupt enable (SIE) bit stores whether maskable interrupts were enabled at the time the first interrupt service routine was entered. Execution of IRET automatically checks the SIE. If the SIE indicates interrupts were enabled, then direct vectoring occurs. If the SIE indicates that interrupts were disabled, then the second interrupt remains pending, and an interrupt return operation is performed by popping the stack and restoring the prior processor state.

Abstract: A hypertext document containing a selection criterion for a desired codeset is transmitted from a web server to a web client on the computer of a user of an electronic consumer device. The user selects a desired codeset and sends a designation of the selection criterion from the web client on his computer back to the web server. The designation of the selection criterion is used to select the desired codeset from a central database of codesets. The desired codeset is then transmitted from the web server to the web client on the user's computer. A pin of an integrated circuit in the user's remote control device is coupled to a single-wire communication bus. The user's remote control device is coupled to the user's computer via the single-wire communication bus. The desired codeset is then transmitted from the user's computer over the single-wire communication bus to the remote control device.

Abstract: Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of the selected input clock signal. Toggle signals are used to control when the output clock signal is to toggle high or low. A latch holds the state of the output clock signal in its current state until changed by receipt of a toggle signal. Switching from use of a first clock signal to use of a second clock signal occurs regardless of whether the first input clock is operating. A delay is introduced that prevents glitches in the output clock signal that are less than one half clock period of the next selected input clock signal in duration.

Abstract: Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of the selected input clock signal. Toggle signals are used to control when the output clock signal is to toggle high or low. A latch holds the state of the output clock signal in its current state until changed by receipt of a toggle signal. Switching from use of a first clock signal to use of a second clock signal occurs regardless of whether the first input clock is operating. A delay is introduced that prevents glitches in the output clock signal that are less than one half clock period of the next selected input clock signal in duration.

Abstract: Program code for a processor is stored in a non-volatile memory (for example, flash memory). An individual data bit stored in a memory cell of the non-volatile memory can be changed from an unprogrammed state to a programmed state using a write cycle. An individual bit stored in the memory cannot, however, be changed from the programmed state back to the unprogrammed state without performing an erase cycle on all the bits of a page of memory cells. The processor has an instruction set that includes a multi-bit breakpoint instruction, all the bits of which are the programmed state. Because all the bits of the breakpoint instruction are the programmed state of the memory, the breakpoint instruction can be written over any other instruction that is stored in the memory without having to perform an erase cycle or erase an entire page of program code.

Abstract: A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.

Abstract: In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

Abstract: A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.

Abstract: A receiving device supplies a remote start bit onto a single-wire communication bus. Open-drain interfaces couple the single-wire communication bus to the receiving device and to a universal asynchronous receiver/transmitter (UART) in the transmitting device. After the UART detects the remote start bit, the UART supplies initial data bits and a stop bit onto the single-wire communication bus. The data bits, stop bit and remote start bit together form a 10-bit RS232 character. Data flow control is accomplished when the receiving device supplies a subsequent remote start bit only after accepting the initial data bits. After the UART detects the subsequent remote start bit on the single-wire communication bus, the UART supplies subsequent data bits onto the single-wire communication bus. The UART also determines a pulse duration of the remote start bit and supplies each of the data bits onto the single-wire communication bus for one pulse duration.

Abstract: Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault detectors. The fault detectors are distributed across the IC and may be embodied in spare cells left in a standard cell IC. Each fault detector is initialized with a digital logic value. The fault detector circuit is then controlled such that the digital logic value stored should not change if the IC is operated under normal operating conditions. An EFT event that is undetected by the power-on reset circuit may, however, cause one of the digital logic values stored in one of the fault detectors to switch. If the digital logic value stored in any one of the fault detectors switches, then a fault signal is provided to the power-on reset circuit that in turn resets the IC.

Abstract: Program code for a Processor is stored in a non-volatile memory (for example, flash memory). An individual data bit stored in a memory cell of the non-volatile memory can be changed from an unprogrammed state to a programmed state using a write cycle. An individual bit stored in the memory cannot, however, be changed from the programmed state back to the unprogrammed state without performing an erase cycle on all the bits of a page of memory cells. The processor has an instruction set that includes a multi-bit breakpoint instruction, all the bits of which are the programmed state. Because all the bits of the breakpoint instruction are the programmed state of the memory, the breakpoint instruction can be written over any other instruction that is stored in the memory without having to perform an erase cycle or erase an entire page of program code.