Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising Silicon and Oxygen and a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer. The build-up layer includes metal pads and metal traces within a dielectric material that are electrically connected to the metal vias of the core layer, the dielectric material comprising Silicon, Oxygen, and at least one of Boron or Phosphorus.

Abstract: In one embodiment, an integrated circuit apparatus (e.g., package substrate) includes a polymeric layer between a metal and a dielectric or between a metal and a glass. The polymeric layer may be conformally deposited using a vacuum-based vapor deposition technique, e.g., initiated chemical vapor deposition (iCVD).