Patents by Inventor Joshua Jia Li

Joshua Jia Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mask layer and dual damascene interconnect structure in a semiconductor device
    Patent number: 7067419
    Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: June 27, 2006
    Assignee: Agere Systems, Inc.
    Inventors: Robert Y S Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt George Steiner, Joseph Ashley Taylor
  • Mask layer and dual damascene interconnect structure in a semiconductor device
    Publication number: 20040121579
    Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
    Type: Application
    Filed: November 25, 2003
    Publication date: June 24, 2004
    Inventors: Robert YS Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt Geroge Steiner, Joseph Ashley Taylor
  • Mask layer and dual damascene interconnect structure in a semiconductor device
    Publication number: 20030119305
    Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Robert Y. S. Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt Geroge Steiner, Joseph Ashley Taylor