Abstract: A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.

Abstract: A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

Abstract: Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Abstract: An advanced encryption standard (AES) engine with real time S-box generation includes a Galois field multiplier system in a first mode responsive to a first data block for generating an AES selection (S-box) function by executing the multiplicative increase in GF1(2m) and applying an affine over GF(2) transformation to obtain a subbyte transformation; and a shift register system for transforming the subbyte transformation to obtain a shift row transformation; the Galois field multiplier system is responsive in a second mode to the shift row transformation to obtain a mix column transformation and add a round key for generating in real time an advanced encryption standard cipher function of the first data block.

Abstract: In a pipeline machine where, in an iterative process, one or more subsequent functions employ one or more parameters determined by one or more antecedent functions and the one or more subsequent functions generate one or more parameters for the one or more antecedent functions, pipeline dependency is reduced by advancing or rotating the iterative process by preliminarily providing to the subsequent function the next one or more parameters on which it is dependent and thereafter: generating by the subsequent function, in response to the one or more parameters on which is it dependent, the next one or more parameters required by the one or more antecedent functions and then, generating by the one or more antecedent functions, in response to the one or more parameters required by the one or more antecedent functions, the next one or more parameters for input to the subsequent function for the next iteration.

Abstract: A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in a Galois field reciprocal generator a first Galois field element by a first element of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m?2 times where m is the degree of the Galois field to obtain the reciprocal of the first Galois field element, and multiplying in the Galois field reciprocal engine the reciprocal of the first Galois field element by a second Galois field element for predicting the modulo remainder of the polynomial product for an irreducible polynomial to obtain the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except t

Abstract: Accommodating a processor to process a number of different data formats includes loading a data word in a first format from a first storage device; reordering, before it reaches the arithmetic unit, the first format of the data word to a second format compatible with the native order of the arithmetic unit; and vector processing the data word in the arithmetic unit.

Abstract: A system for time delay estimation in a discrete time processing system includes a cross correlator that performs cross correlation on a first signal and a second signal, and provides a cross correlated output signals indicative thereof. A lag smoother receives the cross correlated output signals, and provides lag smoothed output signals indicative thereof. A select logic module selects a pre-defined number of signal values from a respective set indicative of the lag smoothed output signals to compute the time delay estimation associated with the first and second signals.

Abstract: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Abstract: Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in at least one deposit-increment index register in the data address generator including a table base field for identifying the location of the set of tables in memory, and a displacement field; and depositing a section of the data word into a displacement field in the index register for identifying the location of a specific entry in the tables.

Abstract: A compact Galois field parallel multiplier engine includes a multiplier circuit for multiplying together two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit has a multiply input from the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; first and second polynomial inputs; the Galois field linear transformer circuit may include a plurality of cells configured in a matrix section and a unity matrix section wherein the unity matrix section cells represent the prediction of the remainder when the output of the multiplier circuit is a polynomial with a power less than the power of the irreducible polynomial.

Abstract: An instruction based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; and applies at least one instruction for enabling indication of at least one of the maximum, minimum, median filter values.

Abstract: An echo canceller includes an adaptive digital filter that generates an estimated echo signal {circumflex over (z)}[k] in response to (i) a sampled input data sequence x[k] and (ii) an error signal sequence e[k] indicative of the difference between a far end signal sequence y[k] and the estimated echo signal {circumflex over (z)}[k]. The adaptive filter includes N filter taps that each provide an associated tap output signal, wherein the adaptive digital filter generates the estimated echo signal {circumflex over (z)}[k] using the associated tap output signals from M of the N filter taps selected in response to a time delay estimate signal. The adaptive filter computes filter coefficients for each of the M number of the N filter taps using the associated tap output signals from the M number of said N filter taps.

Abstract: Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including an index section and a compute section; applying the index section to localized data stored in each compute unit to select one of a plurality of stored local parameter sets; and applying in each compute unit the selected set of parameters to the local data according to the compute section to produce each compute unit's localized solution to the generic instruction.

Abstract: A processing system supporting a secure mode of operation is disclosed. The processing system includes a read-only hardware key that is only accessible in secure mode.

Abstract: A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

Abstract: A video data compression system is disclosed that includes a telecine detection unit and a reverse telecine conversion unit. In accordance with an embodiment, the telecine detection unit receives input video data and produces a telecine detection signal that is representative of whether the input video data is telecine converted video data. The reverse telecine conversion unit converts the input video data and provides reproduced cinematic data responsive to the telecine detection signal. The system also includes an encoder unit for compressing the reproduced cinematic data.

Abstract: A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of symmetry defining four quadrants; and a sequencer circuit for moving the data in each element to the next adjacent element towards one axis of symmetry until the data is in the elements along the one axis of symmetry and then moving the data in the elements along the the one axis of symmetry to the next adjacent element towards the other axis of symmetry until the data is at the four central elements at the origin of the axes of symmetry.

Abstract: A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.

Abstract: An advanced encryption standard (AES) engine with real time S-box generation includes a Galois field multiplier system in a first mode responsive to a first data block for generating an AES selection (S-box) function by executing the multiplicative increase in GF1(2m) and applying an affine over GF(2) transformation to obtain a subbyte transformation; and a shift register system for transforming the subbyte transformation to obtain a shift row transformation; the Galois field multiplier system is responsive in a second mode to the shift row transformation to obtain a mix column transformation and add a round key for generating in real time an advanced encryption standard cipher function of the first data block.