Patents by Inventor Joshua POLZIN

Joshua POLZIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230205614
    Abstract: A method of pipelining execution stages of a pipelined application comprises an application execution program (AEP) utilizing a Pipeline Programming Interface (PPI) of a Buffer Pipelined Application computing System (BPAS). In the method the AEP uses one interface of the PPI to determine buffers, among a set of pipeline buffers stored in physical memories of the BPAS, for the BPAS to execute operations a computing application using batches of application data. The AEP uses a second interface of the PPI to load data batches into pipeline buffers, and a third interface of the PPI to input the buffers to the BPAS for executing operations of the application. The AEP can use another interface of the PPI to allocate the buffers in particular physical memories of the BPAS. A computing system can comprise the AEP and BPAS, and can perform the method.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 29, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Joshua POLZIN, Conrad Alexander TURLIK, Arnav GOEL, Qi ZHENG, Maran WILSON, Neal SANGHVI
  • Publication number: 20230205613
    Abstract: A method of pipelining execution stages of a pipelined application can comprise a Buffer Pipeline Manager (BPM) of a Buffer Pipelined Application computing System (BPAS) allocating pipeline buffers, configuring access to the pipeline buffers by stage processors of the system, transferring buffers from one stage processor to a successor stage processor, and transferring data from a buffer in one memory to a buffer in an alternative memory. The BPM can allocate the buffers based on execution parameters associated with the pipelined application and/or stage processors. The BPM can transfer data to a buffer in an alternative memory based on performance, capacity, and/or topological attributes of the memories and/or processors utilizing the memories. The BPM can perform operations of the method responsive to interfaces of a Pipeline Programming Interface (PPI). A BPAS can comprise hardware processors, physical memories, stage processors, an application execution program, the PPI, and the BPM.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 29, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Joshua POLZIN, Conrad Alexander TURLIK, Arnav GOEL, Qi ZHENG, Maran WILSON, Neal SANGHVI