Abstract: Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.

Abstract: Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.

Abstract: Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.

Abstract: A first vertical transistor device associated with a first conductivity type is formed within a first tier. A second vertical transistor device associated with a second conductivity type is formed within a second tier. The first vertical transistor device is connected to the second vertical transistor device to create a stacked vertical transistor device for three-dimensional monolithic integration such that the first vertical transistor device is located below the second vertical transistor device within the stacked vertical transistor device. Connecting the first vertical transistor device to the second vertical transistor device includes forming interconnects from a top of the second tier to respective positions within the first tier by forming vias and filling the vias with interconnect material.

Abstract: Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.

Abstract: A mobile device includes: a network interface configured to send messages toward, and receive messages from, a communication network wirelessly; and a message module independent of an OS and a BIOS of the mobile device, the message module being configured to produce and provide a location message to the network interface to be sent toward the communication network. The location message contains information that enables at least one of determination or estimation of a location of the mobile device and identification of the mobile device. The message module is configured to provide the location message to the transmitter without use of the operating system or the BIOS. The message module is configured to produce the location message based on a network communication message received at the mobile device through the network interface.

Abstract: The present invention provides chemokine receptor antibodies that selectively bind to an activated form of the receptor but not to a non activated form of the receptor. In particular, the current invention provides phosphospecific chemokine receptor antibodies. The antibodies can be used in several diagnostic, screening and purification methods.

Abstract: The present invention provides a biomarker for a central nervous system inflammatory disorder. The present invention also provides processes for detecting a central nervous system inflammatory disorder and processes for monitoring the effectiveness of a therapeutic treatment for a central nervous system inflammatory disorder.

Abstract: The present invention provides chemokine receptor antibodies that selectively bind to an activated form of the receptor but not to a non activated form of the receptor. In particular, the current invention provides phospho specific chemokine receptor antibodies. The antibodies can be used in several diagnostic, screening and purification methods.

Abstract: A keypad and method for detecting the selection of one of a plurality of key inputs associated with a single key is provided. The keypad includes one or more keys having a primary input selection and three or more secondary input selections. Each secondary input selection has a corresponding switch, where if only one of the switches is engaged when the key is actuated, the corresponding secondary input selection is indicated. If any combination of a plurality of switches are engaged, when the key is actuated, the primary input selection is indicated.