Abstract: A vehicle computing system onboard an autonomous vehicle can include one or more processors and one or more non-transitory computer-readable media that store instructions that, when executed by the one or more processors, cause the computing system to perform operations. The operations can include obtaining sensor data from one or more sensors of the autonomous vehicle; applying lossy compression to the sensor data to generate compressed sensor data; storing data describing the compressed sensor data; decompressing the compressed sensor data to generate decompressed sensor data; and inputting data describing the decompressed sensor data into an autonomy system comprising one or more machine-learned models. The autonomy system can be configured to control operations of the autonomous vehicle based on the decompressed sensor data.

Abstract: Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FPGA) device coupled to the one or more cameras. The FPGA device is configured to implement one or more image processing pipelines for image transformation and object detection. The one or more image processing pipelines can generate a multi-scale image pyramid of multiple image samples having different scaling factors, identify and aggregate features within one or more of the multiple image samples having different scaling factors, access the classification model, provide the features as input to the classification model, and receive an output indicative of objects detected within the image data.

Abstract: Examples are disclosed for using or designing Chien search circuitry to locate errors for error correction code (ECC) encoded data. In some examples, an error locator polynomial (ELP) may be received that indicates a number of possible error locations for ECC encoded data. Chien search circuitry may be designed such that error locations are found based on the received ELP within one or more passes through the search circuitry. The design of the Chien search circuitry to accommodate both an average expected number of error locations for received ELPs and a worst case number of error locations for received ELPs. Other examples are described and claimed.

Abstract: Improved power management techniques for computer-readable storage devices are described. In one embodiment, for example, an apparatus may comprise a plurality of logical storage devices and a controller to manage operations of the plurality of logical storage devices, the controller comprising a configuration component to configure a global power consumption threshold defining an overall power consumption budget for the plurality of logical storage devices, a tracking component to maintain a global power consumption tally comprising an estimated total power consumption level for the plurality of logical storage devices, and an arbitration component to resolve an operation request based on the global power consumption threshold and the global power consumption tally. Other embodiments are described and claimed.

Abstract: Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.

Abstract: Improved power management techniques for computer-readable storage devices are described. In one embodiment, for example, an apparatus may comprise a plurality of logical storage devices and a controller to manage operations of the plurality of logical storage devices, the controller comprising a configuration component to configure a global power consumption threshold defining an overall power consumption budget for the plurality of logical storage devices, a tracking component to maintain a global power consumption tally comprising an estimated total power consumption level for the plurality of logical storage devices, and an arbitration component to resolve an operation request based on the global power consumption threshold and the global power consumption tally. Other embodiments are described and claimed.

Abstract: Examples are disclosed for using or designing Chien search circuitry to locate errors for error correction code (ECC) encoded data. In some examples, an error locator polynomial (ELP) may be received that indicates a number of possible error locations for ECC encoded data. Chien search circuitry may be designed such that error locations are found based on the received ELP within one or more passes through the search circuitry. The design of the Chien search circuitry to accommodate both an average expected number of error locations for received ELPs and a worst case number of error locations for received ELPs. Other examples are described and claimed.

Abstract: Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.

Abstract: Method and system are provided for handling data when power failure from a primary power source of a storage system is detected. The system provides a first memory and a second memory. The first memory is primarily used to store data when the primary power source is operating. If a power failure is detected, a first indicator is set to indicate that data is stored or being transferred to the second memory. Thereafter, data is transferred from the first memory to the second memory. Any errors during the transfer are logged. Once power is restored, data is transferred back to the first memory. A second indicator is set to indicate that there is no data at the second memory.

Abstract: A system and method for batch signing of a message is provided. An administrator initiates a management operation directed to a plurality of security appliances organized as a cluster. In response, the security appliance generates an operation context identifying the management operation to be performed. In addition, a secure encryption processor (SEP) of each security appliance generates a random nonce. The nonces are then assembled along with the operation context into a single message. The message is then cryptographically signed by an appropriate number of administrators using a cryptographic key associated with each administrator. The signed message is returned to the security appliances, where each security appliance examines the signed message and determines whether its nonce is present within the message. If so, the security appliance performs the desired management operation. However, if its nonce is not present in the signed message, the management operation is disallowed and not performed.

Abstract: The invention provides an authentication scheme that allows networked devices to establish trust in connection with the exchange of keys pursuant to an asymmetrical cryptographic technique, such as Diffie-Hellman. The invention provides a technique, referred to as offline key establishment, that establishes a trust relationship between two networked devices that use Diffie-Helman. Offline key sharing provides for the exchange of authentication information using a separate channel which, in the preferred embodiment does not constitute an IP connection. Thus, while communications between networked devices may ultimately proceed via a network connection, trust between the networked devices is established via a separate, offline channel, such as a telephone call or email message. The use of offline key establishment allows for such features as one way key sharing; and addresses situations where one party to the exchange does not want to share all of his keys, but just one or two keys.