Patents by Inventor Joshua Stacey
Joshua Stacey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112140Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Rahul BHURE, Mitchell PAGE, Joseph PEOPLES, Jieying KONG, Nicholas S. HAEHN, Astitva TRIPATHI, Bainye Francoise ANGOUA, Yosef KORNBLUTH, Daniel ROSALES-YEOMANS, Joshua STACEY, Aaditya Anand CANDADAI, Yonggang Yong LI, Tchefor NDUKUM, Scott COATNEY, Gang DUAN, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Dilan SENEVIRATNE, Matthew ANDERSON
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Publication number: 20250112175Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
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Publication number: 20250112163Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Pratyush Mishra, Pratyasha Mohapatra, Srinivas Pietambaram, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Yosef Kornbluth, Kuang Liu, Astitva Tripathi, Yuqin Li, Rengarajan Shanmugam, Xing Sun, Brian Balch, Darko Grujicic, Jieying Kong, Nicholas Haehn, Jacob Vehonsky, Mitchell Page, Vincent Obiozo Eze, Daniel Wandera, Sameer Paital, Gang Duan
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Patent number: 12266581Abstract: An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.Type: GrantFiled: October 30, 2020Date of Patent: April 1, 2025Assignee: Intel CorporationInventors: Joshua Stacey, Whitney Bryks, Sarah Blythe, Peumie Abeyratne Kuragama, Junxin Wang
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Patent number: 12214579Abstract: The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations across a substrate panel and the controller may adjust the temperature output of the heating and cooling elements to locally modify the viscosity of the laminating material in one or more regions of the substrate panel to either decrease or increase the flowability of the laminating material.Type: GrantFiled: September 21, 2022Date of Patent: February 4, 2025Assignee: INTEL CORPORATIONInventors: Joshua Stacey, Yosef Kornbluth, Whitney Bryks
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Publication number: 20240222295Abstract: Embodiments described herein enable a microelectronic assembly that includes: a package substrate having a core including a solid continuous glass material with one or more capacitors in the solid continuous glass material and integrated circuit (IC) dies coupled to the package substrate. The structure of each capacitor includes a dielectric structure between two conductive structures. The dielectric structure comprises a layer of organic dielectric material between two layers of crystalline inorganic material. The crystalline inorganic material is in direct contact with one of the two conductive structures.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Mahdi Mohammadighaleni, Joshua Stacey, Benjamin T. Duong, Thomas S. Heaton, Dilan Seneviratne, Rahul N. Manepalli
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Publication number: 20240173953Abstract: The present disclosure is directed to an apparatus including a first laminating component configured to laminate a dry film onto a substrate using heat, and a focused cure module configured to selectively cure a first portion of the dry film without curing a second portion of the dry film. The first portion forms a perimeter that surrounds the second portion.Type: ApplicationFiled: November 30, 2022Publication date: May 30, 2024Inventors: Joshua STACEY, Thomas HEATON, Dilan SENEVIRATNE
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Publication number: 20240105476Abstract: The present disclosure is directed to a coating module including: a coating stage and a plurality of vertical guides configured to perpendicularly extend from the coating stage; a vertical movement mechanism configured to lower a framed panel along the plurality of vertical guides onto the coating stage; an optical alignment tool configured to provide feedback on a lateral alignment between an edge of the coating stage and the framed panel; and a dispensing unit configured to coat a surface of the panel.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Whitney BRYKS, Thomas HEATON, Joshua STACEY, Dilan SENEVIRATNE, Cansu ERGENE
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Publication number: 20240092074Abstract: The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations across a substrate panel and the controller may adjust the temperature output of the heating and cooling elements to locally modify the viscosity of the laminating material in one or more regions of the substrate panel to either decrease or increase the flowability of the laminating material.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Inventors: Joshua STACEY, Yosef KORNBLUTH, Whitney BRYKS
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Publication number: 20240096561Abstract: An apparatus, system, and method for in-situ three-dimensional (3D) thin-film capacitor (TFC) are provided. A 3D TFC can include a glass core, a through glass via (TGV) in the glass core including first conductive material, the first conductive material forming a first electrode of the 3D MIM capacitor, a second conductive material acting as a second electrode of the 3D MIM capacitor, and a dielectric material in contact with the first and second conductive materials, the dielectric material extending vertically and horizontally and physically separating the first and second conductive materials.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Mahdi Mohammadighaleni, Benjamin Duong, Shayan Kaviani, Joshua Stacey, Miranda Ngan, Dilan Seneviratne, Thomas Heaton, Srinivas Venkata Ramanuja Pietambaram, Whitney Bryks, Jieying Kong
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Publication number: 20240079530Abstract: Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Jacob VEHONSKY, Onur OZKAN, Vinith BEJUGAM, Mao-Feng TSENG, Nicholas HAEHN, Andrea NICOLAS FLORES, Ali LEHAF, Benjamin DUONG, Joshua STACEY
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Publication number: 20220139792Abstract: An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: Joshua Stacey, Whitney Bryks, Sarah Blythe, Peumie Abeyratne Kuragama, Junxin Wang
