Patents by Inventor Joshua Taylor
Joshua Taylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143445Abstract: Stability testing for memory overclocking is described. In accordance with the described techniques, operation of a memory with overclocked memory settings is testing during a boot up process of a computing device. Test results based on the testing are exposed via a user interface. The test results predict a stability of the memory over a subsequent time period if the memory is configured to operate with the overclocked memory settings.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Alicia Wen Ju Yurie Leong, William Robert Alverson, Joshua Taylor Knight, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Amitabh Mehra, Jayesh Hari Joshi
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Patent number: 11972652Abstract: The secured storage receives an electronic device including but not limited to a tablet, smart phone, mobile computing device, or other computing device. The secured storage provides a charging system that charges the device. The system selectively charges the devices based upon identified rules. The lock of the secured storage secures the electronic device within the storage. The system maintains a log of the users who access the electronic devices. The system then control access by granting access to users and restricting access to users based upon usage history, behavior, or other criteria.Type: GrantFiled: June 9, 2020Date of Patent: April 30, 2024Assignee: TECH FRIENDS, INC.Inventors: Bobby L. Shipman, Jr., Bryan Taylor, Jason Cochran, Joshua L. Parrish, Mark Haney, Bobby L. Shipman, III
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Patent number: 11964422Abstract: Described herein are various embodiments of a valve that may be opened and closed using a thixotropic or “stress yield” material, or other material that temporarily changes phase upon application of energy to the material. More particularly, some embodiments may include a valve that is opened and closed using a granular gel that is a temporary phase change material.Type: GrantFiled: April 30, 2021Date of Patent: April 23, 2024Assignee: University of Florida Research Foundation, Inc.Inventors: Joshua Muse, Meghan Hughes, Carl David Crane, Thomas Ettor Angelini, Kyle D. Schulze, Tapomoy Bhattacharjee, Wallace Gregory Sawyer, Curtis Taylor
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Publication number: 20240108951Abstract: An iron-type golf club head is provided with a body having a volume less than 120 cc. The body can include a sole portion with two or more slots extending upwardly into the body through the sole portion into a cavity behind a face portion. A damper can be included in the cavity and in contact with a rear surface of the face portion. The club head can have a maximum CT proximate to the ideal striking location and a CT dropoff of no more than 110 ?s at a point located between a first and second scoreline proximate to the sole portion. The club head can also have a CG along the y-axis (CG-y) between 0.25 mm and 20 mm and a CG along a positive z-up axis (CG-z) between 12 mm and 25 mm.Type: ApplicationFiled: September 29, 2023Publication date: April 4, 2024Applicant: Taylor Made Golf Company, Inc.Inventors: Scott Taylor, Peter L. Larsen, Bret H. Wahl, Joshua J. Dipert
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Publication number: 20240075356Abstract: Disclosed herein are embodiments of iron-type golf club heads that include weight reducing features in the topline region of the club head that facilitate changing the Z-up location of the club head. In some embodiments the body includes a weight reducing feature in a topline weight reduction zone of the club head that extends over the entire face length from the par line to the toe portion ending at approximately the Z-up location of the iron type golf club head. The weight reducing feature results in a mass savings of about 2 g to about 20 g, and a Zup shift of about 0.5 mm to about 2.0 mm.Type: ApplicationFiled: September 15, 2023Publication date: March 7, 2024Applicant: Taylor Made Golf Company, Inc.Inventors: Jason W. Issertell, Joshua J. Dipert, Bret H. Wahl, Maresala Milo, Zac Atwell, Scott Taylor
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Publication number: 20240053891Abstract: Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage solution without reducing the amount of system memory available to an operating system running on the one or more processing units.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Applicant: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Patent number: 11835998Abstract: Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.Type: GrantFiled: June 29, 2021Date of Patent: December 5, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Amitabh Mehra, Jerry A. Ahrens, Anil Harwani, Richard Martin Born, Dirk J. Robinson, William R. Alverson, Joshua Taylor Knight
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Publication number: 20230350696Abstract: Real time workload-based system adjustment is described. In accordance with the described techniques, a processor and a memory are operated according to first settings associated with a first workload. A second workload configured to utilize the processor and the memory is detected. The second workload is associated with second settings. Responsive to detecting the second workload, operation of the processor and the memory are adjusted to operate according to the second settings without rebooting.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Anil Harwani, William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Joshua Taylor Knight
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Publication number: 20230350591Abstract: Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Grant Evan Ley, Jayesh Hari Joshi, Amitabh Mehra, Jerry Anton Ahrens, Joshua Taylor Knight, Anil Harwani, William Robert Alverson
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Publication number: 20230350715Abstract: Various timing parameter values for a memory system are changed and a workload is run using the changed timing parameter values resulting in workload performance values. The workload is run multiple times with different timing parameter values and the performance values generated by the workload are used to generate and output a performance indication that identifies how sensitive performance of the physical memory is to the one or more timing parameters. The parameter values generated by the workload are optionally used to predict what parameter value the workload would have generated for user selected timing parameter values (e.g., without running the workload).Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Joshua Taylor Knight, Jayesh Hari Joshi, Anil Harwani, Grant Evan Ley, Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra
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Patent number: 11802045Abstract: High temperature moderators for nuclear reactors and processes for their production are disclosed. The moderators include at least one hydrided metal and/or hydride metal allow, such as yttrium hydride, thorium hydride, yttrium-cerium hydride, yttrium-gadolinium hydride, yttrium calcium hydride, cerium hydride, etc. Such metal hydrides and/or hydride alloys may have high thermal stability, a relatively low thermal neutron absorption cross section, the ability to retain hydrogen over a large temperature range, and have good mechanical properties. Such moderators may induce spectral shift in reactors which, in turn, magnifies the Doppler reactivity temperature coefficient. Such moderators to thermalize neutrons may also enhance fuel utilization and cost-effectiveness of the reactor while keeping the core portable.Type: GrantFiled: May 29, 2020Date of Patent: October 31, 2023Assignee: TRIAD NATIONAL SECURITY, LLCInventors: Venkateswara Rao Dasari, Erik Luther, Dustin Cummins, Tarik Saleh, Joshua Taylor White, Joseph Wermer, Aditya Shivprasad, A.J. Fallgren
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Publication number: 20230324947Abstract: User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings.Type: ApplicationFiled: March 25, 2022Publication date: October 12, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Amitabh Mehra, William Robert Alverson, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Publication number: 20230324967Abstract: Package lids with carveouts configured to expose lights directly connected to an internal component of a processor are described. Lid carveouts are configured to precisely align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device via a press fit connection, while maintaining visibility of lights directly connected to processor internal components when the cooling device is connected. Lid carveouts are further configured to expose one or more connectors disposed on a processor surface that supports its internal component. When contacted by corresponding connectors of an auxiliary device, such as a light not integrated into a processor package or a cooling device, the lid carveouts enable direct connections between the package’s internal components and the auxiliary device.Type: ApplicationFiled: March 25, 2022Publication date: October 12, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Publication number: 20230315191Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Publication number: 20230315171Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.Type: ApplicationFiled: March 25, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Patent number: 11777252Abstract: A manufacturing method for assembling a high voltage vertical disk ferrule, the ferrule being stamped and having a vertical disk-like structure, which is not necessarily round or does not necessarily have any roundness. The high voltage disk ferrule has an opening residing and traveling over the wire core and/or a wire braided shield, to which an end portion of the wire braided shield is affixed thereto the ferrule, or between two ferrules, such that a portion of the wire braided shield is flared and substantially perpendicular to the direction along which the wire core extends. The high voltage vertical disk ferrule slides over the core insulation, towards the outer insulation when the wire is pushed. The end portion/flared portion of the braided shield and the high voltage vertical disk ferrule, or the end portion/flared portion of the braided shield between at least two high voltage vertical disk ferrules are soldered, welded, or brazed together.Type: GrantFiled: July 2, 2021Date of Patent: October 3, 2023Assignee: J.S.T. CORPORATIONInventors: David Demaratos, Joshua Taylor
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Patent number: 11670892Abstract: A high voltage vertical disk ferrule, and method for assembling thereof, the ferrule being stamped and having a vertical disk-like structure, which is not necessarily round or does not necessarily have any roundness. The high voltage vertical disk ferrule has an opening residing and traveling over the wire core and/or a wire braided shield, to which an end portion of the wire braided shield is affixed to the ferrule, or between two ferrules, such that a portion of the wire braided shield is flared and substantially perpendicular to the direction along which the wire core extends. The high voltage vertical disk slides over the core insulation, and towards the outer insulation when the wire is pushed. The wire braided shield develops a natural spring force against the ferrule, and causes it to be accordioned, pleated, or folded against itself, and therefore pushes the vertical disk ferrule forward.Type: GrantFiled: November 23, 2020Date of Patent: June 6, 2023Assignee: J.S.T. CORPORATIONInventors: David Demaratos, Joshua Taylor
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Publication number: 20220413543Abstract: Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Inventors: Amitabh Mehra, Jerry A. Ahrens, Anil Harwani, Richard Martin Born, Dirk J. Robinson, William R. Alverson, Joshua Taylor Knight
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Patent number: 11381030Abstract: A method for reducing the effect of electromagnetic interference (EMI), providing EMI protection to a connector assembly, using at least one vertical disk ferrule. The method includes steps of providing a flared portion, first portion, of a wire shield to at least a vertical disk ferrule, or affixing between two of said vertical disk ferrules. Further, one of a step of providing a ferrule having a face which contacts a metallic connector housing directly; or providing the flared portion of the wire shield which contacts said metallic connector housing directly; wherein said EMI is conducted from said metallic connector housing to said ferrule or flared portion, further conducting said EMI to said flared portion of the wire shield, further conducting said EMI through a second portion of said wire shield, further conducting said EMI to ground; said EMI being generated by at least the metallic connector housing.Type: GrantFiled: December 11, 2020Date of Patent: July 5, 2022Assignee: J.S.T. CORPORATIONInventors: David Demaratos, Joshua Taylor
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Publication number: 20220021161Abstract: A method for reducing the effect of electromagnetic interference (EMI), providing EMI protection to a connector assembly, using at least one vertical disk ferrule. The method includes steps of providing a flared portion, first portion, of a wire shield to at least a vertical disk ferrule, or affixing between two of said vertical disk ferrules. Further, one of a step of providing a ferrule having a face which contacts a metallic connector housing directly; or providing the flared portion of the wire shield which contacts said metallic connector housing directly; wherein said EMI is conducted from said metallic connector housing to said ferrule or flared portion, further conducting said EMI to said flared portion of the wire shield, further conducting said EMI through a second portion of said wire shield, further conducting said to ground; said EMI being generated by at least the metallic connector housing.Type: ApplicationFiled: December 11, 2020Publication date: January 20, 2022Applicant: J.S.T. CORPORATIONInventors: David DEMARATOS, Joshua TAYLOR