Patents by Inventor Joshua W. Bowman
Joshua W. Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11403109Abstract: A computer system, processor, and method for processing information is disclosed that includes reading out a plurality of entries in a history buffer prior to initiating a flush recovery process; initiating the flush recovery process; determining which of the history buffer entries read out of the history buffer should be recovered; and sending information associated with the history buffer entries to be recovered to one or more history buffer recovery ports. In one or more embodiments, the history buffer entries are continually read out in response to a processor and history buffer entries read out from the history buffer are directed to a specific history buffer recovery port associated with a mapper of a specific logical register.Type: GrantFiled: December 5, 2018Date of Patent: August 2, 2022Assignee: International Business Machines CorporationInventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
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Patent number: 11360779Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.Type: GrantFiled: December 2, 2020Date of Patent: June 14, 2022Assignee: International Business Machines CorporationInventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Christopher M. Mueller, Dung Q. Nguyen
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Patent number: 11301254Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream, detecting a branch instruction in the parent stream, activating an additional child stream, copying the content of a parent mapper copy of the parent stream to an additional child mapper copy, dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, a first parent mapper copy is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream. The method in an aspect includes processing one or more streams and/or one or more threads of execution on one or more execution slices.Type: GrantFiled: July 25, 2019Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
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Patent number: 11194578Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, preferably a condition register that stores status information, the register file having multiple locations for storing data, multiple ports to write data to and read data from the register file. The system or processor includes an execution area, and the processor is configured to read from all the read ports in a first cycle, and to read from all the read ports in a second cycle. In an embodiment, the execution area includes a staging latch to store data from a first cycle read operation, and in an aspect the computer system is configured to combine the data stored in the staging latch during a first read cycle with the data read from the second cycle.Type: GrantFiled: May 23, 2018Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Steven J. Battle, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Cliff Kucharski, Dung Q. Nguyen, David S. Walder
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Patent number: 11188332Abstract: A method, processor and/or system for processing data is disclosed that in an aspect includes providing a physical register file with one or more register file entries for storing data; identifying each physical register file entry with a row identifier to identify the entry row in the physical register file; enabling one or more columns within a target entry row of the physical register file; and revising data in the columns enabled within the target entry row of the physical register file. In an aspect, each physical register file entry is partitioned into a plurality of columns having a bit width and a column mask preferably is used to enable the one or more columns within the target row of the physical register file, and data is revised in only the columns enabled by the column mask.Type: GrantFiled: May 10, 2019Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Cliff Kucharski, Dung Q. Nguyen
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Patent number: 11144364Abstract: Recovering microprocessor logical register values by: partitioning a register mapper by logical register type; providing a plurality of recovery ports; assigning a logical register type to a recovery port; receiving a restore required instruction; and mapping SRB (save and restore buffer) values to the register mapper by logical register type.Type: GrantFiled: January 25, 2019Date of Patent: October 12, 2021Assignee: International Business Machines CorporationInventors: Steven J. Battle, Brandon R. Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick, Susan E. Eisen, David S. Walder, Cliff Kucharski
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Patent number: 11093282Abstract: A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.Type: GrantFiled: April 15, 2019Date of Patent: August 17, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
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Patent number: 11068267Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.Type: GrantFiled: April 24, 2019Date of Patent: July 20, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick, Susan Eisen, Salma Ayub, Christopher M. Mueller
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Patent number: 11061681Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream; detecting a branch instruction in the parent stream; activating an additional child stream; setting a copy select vector of the child stream to be the same as the copy select vector of the parent stream; dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, the method further includes setting the copy select bits in the copy select vector for the child stream to equal the copy select bits in the copy select vector for the parent stream. A first parent mapper copy in an embodiment is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream.Type: GrantFiled: July 25, 2019Date of Patent: July 13, 2021Assignee: International Business Machines CorporationInventors: Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q Nguyen, Brian W. Thompto
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Publication number: 20210089322Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Inventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Christopher M. Mueller, Dung Q. Nguyen
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Patent number: 10956158Abstract: A method, processor and system for processing data is disclosed that includes evicting one or more evicted fields from a logical register mapper; receiving, by a history buffer, the one or more evicted fields from the logical register mapper; determining whether two or more of the evicted fields from the mapper qualify to be written to a single entry in the history buffer; and in response to the two or more evicted fields qualifying, writing the two or more qualifying evicted fields received from the mapper to a single entry in the qualified history buffer. The method, processor, and/or system further includes in an embodiment, remapping the one or more qualified evicted fields, and further, in response to the two or more evicted fields not qualifying to be written to a single entry in the history buffer, writing the two or more evicted fields to multiple history buffer entries.Type: GrantFiled: May 10, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Thao T. Doan, Susan E. Eisen, Brandon Goddard, Dung Q. Nguyen
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Patent number: 10949213Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.Type: GrantFiled: December 5, 2018Date of Patent: March 16, 2021Assignee: International Business Machines CorporationInventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Christopher M. Mueller, Dung Q. Nguyen
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Patent number: 10936321Abstract: An approach is disclosed that that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instrucType: GrantFiled: February 1, 2019Date of Patent: March 2, 2021Assignee: International Business Machines CorporationInventors: Kurt A. Feiste, Joshua W. Bowman, Christopher M. Mueller, Dung Q. Nguyen, Deepak K. Singh, Brian W. Thompto
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Patent number: 10909034Abstract: Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.Type: GrantFiled: December 18, 2017Date of Patent: February 2, 2021Assignee: International Business Machines CorporationInventors: David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle, Sundeep Chadha, Brian D. Barrick, Albert J. Van Norstrand, Jr.
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Publication number: 20210026642Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream, detecting a branch instruction in the parent stream, activating an additional child stream, copying the content of a parent mapper copy of the parent stream to an additional child mapper copy, dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, a first parent mapper copy is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream. The method in an aspect includes processing one or more streams and/or one or more threads of execution on one or more execution slices.Type: ApplicationFiled: July 25, 2019Publication date: January 28, 2021Inventors: Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
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Publication number: 20210026643Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream; detecting a branch instruction in the parent stream; activating an additional child stream; setting a copy select vector of the child stream to be the same as the copy select vector of the parent stream; dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, the method further includes setting the copy select bits in the copy select vector for the child stream to equal the copy select bits in the copy select vector for the parent stream. A first parent mapper copy in an embodiment is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream.Type: ApplicationFiled: July 25, 2019Publication date: January 28, 2021Inventors: Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
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Publication number: 20200356369Abstract: A method, processor and/or system for processing data is disclosed that in an aspect includes providing a physical register file with one or more register file entries for storing data; identifying each physical register file entry with a row identifier to identify the entry row in the physical register file; enabling one or more columns within a target entry row of the physical register file; and revising data in the columns enabled within the target entry row of the physical register file. In an aspect, each physical register file entry is partitioned into a plurality of columns having a bit width and a column mask preferably is used to enable the one or more columns within the target row of the physical register file, and data is revised in only the columns enabled by the column mask.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Inventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Cliff Kucharski, Dung Q. Nguyen
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Publication number: 20200356366Abstract: A method, processor and system for processing data is disclosed that includes evicting one or more evicted fields from a logical register mapper; receiving, by a history buffer, the one or more evicted fields from the logical register mapper; determining whether two or more of the evicted fields from the mapper qualify to be written to a single entry in the history buffer; and in response to the two or more evicted fields qualifying, writing the two or more qualifying evicted fields received from the mapper to a single entry in the qualified history buffer. The method, processor, and/or system further includes in an embodiment, remapping the one or more qualified evicted fields, and further, in response to the two or more evicted fields not qualifying to be written to a single entry in the history buffer, writing the two or more evicted fields to multiple history buffer entries.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Inventors: Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Thao T. Doan, Susan E. Eisen, Brandon Goddard, Dung Q. Nguyen
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Publication number: 20200341767Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.Type: ApplicationFiled: April 24, 2019Publication date: October 29, 2020Inventors: Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick, Susan Eisen, Salma Ayub, Christopher M. Mueller
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Publication number: 20200326978Abstract: A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.Type: ApplicationFiled: April 15, 2019Publication date: October 15, 2020Inventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry