Patents by Inventor Josine Loo

Josine Loo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8452369
    Abstract: The present invention provides an electronic device for sensing and/or actuating, the electronic device comprising at least one microneedle (10) on a substrate (1), each of the microneedles (10) comprising at least one channel (7, 8) surrounded by an insulating layer (6). The present invention also provides a method for making such an electronic device for sensing and/or actuating.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: May 28, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Roeland Huys, Carmen Bartic, Josine Loo
  • Patent number: 7838367
    Abstract: The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20) being executed from the first side of the semiconductor body (2) through and on both sides of the first gate electrode (7), which implantation results in a change of property of the silicon below the first gate electrode (7) compared to the silicon on both sides of the gate electrode 7) in a section of the channel region (5) remote from the first gate dielectric (6A), and on the second surface of the semiconductor body (2) a cavity (30) being provided therein by means of selective etching while use is made of the change of property of the silicon. A second gate (6B,8) is deposited in the cavity thus formed.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: November 23, 2010
    Assignee: NXP B.V.
    Inventors: Youri Ponomarev, Josine Loo
  • Publication number: 20100264492
    Abstract: A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions (38, 40), activated source and drain regions (30, 32) and a body region (34). The structure may be a double gated SOI structure or a fully depleted (FD) SOI structure. A sharp intergace and low resistance are achieved with a process that uses spacers (28) and which fully replaces the full thickness of a semiconductor layer with the contact regions.
    Type: Application
    Filed: June 6, 2006
    Publication date: October 21, 2010
    Inventors: Radu Surdeanu, Gerben Doornbos, Youri Ponomarev, Josine Loo
  • Publication number: 20080319298
    Abstract: The present invention provides an electronic device for sensing and/or actuating, the electronic device comprising at least one microneedle (10) on a substrate (1), each of the microneedles (10) comprising at least one channel (7, 8) surrounded by an insulating layer (6). The present invention also provides a method for making such an electronic device for sensing and/or actuating.
    Type: Application
    Filed: March 6, 2008
    Publication date: December 25, 2008
    Applicants: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Roeland Huys, Carmen Bartic, Josine Loo
  • Patent number: 7407844
    Abstract: A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: August 5, 2008
    Assignee: NXP B.V.
    Inventors: Josine Loo, Youri Ponomarev
  • Publication number: 20080093668
    Abstract: The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20) being executed from the first side of the semiconductor body (2) through and on both sides of the first gate electrode (7), which implantation results in a change of property of the silicon below the first gate electrode (7) compared to the silicon on both sides of the gate electrode (7) in a section of the channel region (5) remote from the first gate dielectric (6A), and on the second surface of the semiconductor body (2) a cavity (30) being provided therein by means of selective etching while use is made of the change of property of the silicon. A second gate (6B,8) is deposited in the cavity thus formed.
    Type: Application
    Filed: December 19, 2005
    Publication date: April 24, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Youri Ponomarev, Josine Loo
  • Publication number: 20070232003
    Abstract: A method of fabricating a dual-gate semiconductor device is provided in which wsilicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.
    Type: Application
    Filed: May 25, 2005
    Publication date: October 4, 2007
    Inventors: Josine Loo, Youri Ponomarev